Abstract: Passivation films 3a, 3b are formed to cover both surfaces of semiconductor substrate 1 which comprises terminal pads 2a, 2b on both surfaces. Openings 3c, 3d are provided at positions on passivation films 3a. 3b which match with terminal pads 2a, 2b. Throughholes 9 are formed inside of openings 3c, 3d to extend through terminal pad 2a, semiconductor substrate 1, and terminal pad 2b. Insulating layer 4 made of SiO2, SiN, SiO, or the like is formed on the inner surfaces of throughholes 9. Buffer layer 5 made of a conductive adhesive is formed to cover insulating layer 4 and terminal pads 2a, 2b in openings 3c, 3d. Further, conductive layer 6 made of a metal film is formed on buffer layer 5 by electrolytic plating, non-electrolytic plating, or the like.

Abstract: Passivation films 3a, 3b are formed to cover both surfaces of semiconductor substrate 1 which comprises terminal pads 2a, 2b on both surfaces. Openings 3c, 3d are provided at positions on passivation films 3a, 3b which match with terminal pads 2a, 2b. Throughholes 9 are formed inside of openings 3c, 3d to extend through terminal pad 2a, semiconductor substrate 1, and terminal pad 2b. Insulating layer 4 made of SiO2, SiN, SiO, or the like is formed on the inner surfaces of throughholes 9. Buffer layer 5 made of a conductive adhesive is formed to cover insulating layer 4 and terminal pads 2a, 2b in openings 3c, 3d. Further, conductive layer 6 made of a metal film is formed on buffer layer 5 by electrolytic plating, non-electrolytic plating, or the like.