Patents by Inventor Sakae Takei

Sakae Takei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of making a semiconductor read only memory
    Patent number: 4565712
    Abstract: A semiconductor read only memory having a plurality of MOS transistors and polycrystalline or amorphous silicon resistances connected to the source or drain regions of the MOS transistors, laser beams irradiating selected silicon resistances to thermally activate those resistances and store the required data.
    Type: Grant
    Filed: May 23, 1984
    Date of Patent: January 21, 1986
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Hideo Noguchi, Tugunari Iwamoto, Sakae Takei
  • Semiconductor read only memory and method of making the same
    Patent number: 4476478
    Abstract: A semiconductor read only memory having a plurality of MOS transistors and polycrystalline or amorphous silicon resistances connected to the source or drain regions of the MOS transistors, laser beams irradiating selected silicon resistances to thermally activate those resistances and store the required data.
    Type: Grant
    Filed: March 19, 1981
    Date of Patent: October 9, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Hideo Noguchi, Tugunari Iwamoto, Sakae Takei
  • Semiconductor integrated circuit device with dual thickness poly-silicon wiring
    Patent number: 4162506
    Abstract: A semiconductor integrated circuit device consisting of silicon gate MOS transistors. A polycrystalline silicon wiring layer is formed on a field insulating layer and connected with a polycrystalline gate electrode layer having a smaller thickness than that of the wiring layer, whereby the resistance of the wiring layer is reduced without making the gate electrode layer thick.
    Type: Grant
    Filed: July 10, 1978
    Date of Patent: July 24, 1979
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventor: Sakae Takei
  • Method for manufacturing monolithic semiconductor mask programmable ROM's
    Patent number: 4129936
    Abstract: A method for manufacturing ROM's composed of a plurality of matrix-arranged IGFET's comprises a process for manufacturing a semiconductor device with no information yet written therein and a process for completing the ROM by writing predetermined information or memory in the no-information semiconductor device according to orders from users.
    Type: Grant
    Filed: September 8, 1977
    Date of Patent: December 19, 1978
    Inventor: Sakae Takei