Patents by Inventor Sake Buwalda

Sake Buwalda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260032365
    Abstract: Various example embodiments for supporting burst mode communications in an optical communication system may be configured to support burst mode communications based on use of a burst delineation scheme for burst detection. The burst delineation scheme may be based on detection of a delimiter in a burst mode transmission based on selecting, from a received bit stream, a first and second sets of bits, computing first and second error statistics on the first and second sets of bits, computing one or more error metrics based on one or more linear combinations of the first and second error statistics, and determining, based on one or more comparisons based on the one or more error metrics and one or more error thresholds, whether the received bit stream includes a delimiter. The burst delineation scheme for burst detection may be used for burst detection within various types of optical communication networks, including passive optical networks.
    Type: Application
    Filed: July 25, 2024
    Publication date: January 29, 2026
    Inventors: Amitkumar Mahadevan, Yannick Lefevre, Werner Van Hoof, Koenraad Schelfhout, Sake Buwalda
  • Patent number: 7917819
    Abstract: A test-communication path is provided between chips in a multi-chip package. Externally-accessible JTAG input and output pins are provided to a first chip in the multi-chip package, and this first chip is configured to allow signals received on these JTAG pins to be routed to other chips in the multi-chip package. Control signals provided to the first chip control the routing of the JTAG signals to each chip.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: March 29, 2011
    Assignee: NXP B.V.
    Inventors: Jacky Talayssat, Sake Buwalda
  • Publication number: 20080288839
    Abstract: A test-communication path is provided between chips in a multi-chip package. Externally-accessible JTAG input and output pins are provided to a first chip in the multi-chip package, and this first chip is configured to allow signals received on these JTAG pins to be routed to other chips in the multi-chip package. Control signals provided to the first chip control the routing of the JTAG signals to each chip.
    Type: Application
    Filed: January 5, 2005
    Publication date: November 20, 2008
    Applicant: NXP B.V.
    Inventors: Jacky Talayssat, Sake Buwalda