Patents by Inventor Saket Arun Jamkar

Saket Arun Jamkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8839006
    Abstract: Power management systems and methods that facilitate efficient and effective power conservation are presented. In one embodiment a power management method comprises: performing an initiation metric determination process, and adjusting operations of a logic component based on said threshold value. In one exemplary implementation, the initiation metric determination process includes monitoring activity of a logic component, and establishing a power conservation initiation threshold value. The initiation metric determination process can include performing a system architecture characteristic analysis in which a system architecture power-consumption break-even time (BE) is determined for the system. The initiation metric determination process can also include performing a system utilization analysis process is performed in which idle period durations detected during said monitoring are sorted into a variety of different length intervals and analyzed accordingly.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: September 16, 2014
    Assignee: Nvidia Corporation
    Inventors: Sau Yan Keith Li, Thomas Edward Dewey, Saket Arun Jamkar, Amit Parikh
  • Patent number: 8762761
    Abstract: An integrated circuit, in accordance with embodiments of the present technology, includes a plurality of engines, a plurality of engine level power gating (ELPG) controllers, and a power gating arbiter for implementing engine level power gating arbitration techniques. The power gating arbiter may receive requests from one or more ELPG controllers to turn on their respective engines or portions therein. The power gating arbiter prioritizes the request and sends an acknowledgment to a given ELPG controller to turn on or off its corresponding engine according to the prioritized predetermined order. After receiving the acknowledgement, the given ELPG controller turns on or off its corresponding engine and returns an indication to the power gating arbiter that the corresponding engine is turned on or off. The process may be iteratively repeated for each received request after receiving the indication from the previously serviced ELPG controller that its corresponding engine is turned on or off.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: June 24, 2014
    Assignee: Nvidia Corporation
    Inventors: Zheng Yu Zheng, Oren Rubinstein, Yudong Tan, Saket Arun Jamkar, Yogesh Kulkarni
  • Publication number: 20120146706
    Abstract: An integrated circuit, in accordance with embodiments of the present technology, includes a plurality of engines, a plurality of engine level power gating (ELPG) controllers, and a power gating arbiter for implementing engine level power gating arbitration techniques. The power gating arbiter may receive requests from one or more ELPG controllers to turn on their respective engines or portions therein. The power gating arbiter prioritizes the request and sends an acknowledgment to a given ELPG controller to turn on or off its corresponding engine according to the prioritized predetermined order. After receiving the acknowledgement, the given ELPG controller turns on or off its corresponding engine and returns an indication to the power gating arbiter that the corresponding engine is turned on or off. The process may be iteratively repeated for each received request after receiving the indication from the previously serviced ELPG controller that its corresponding engine is turned on or off.
    Type: Application
    Filed: December 10, 2010
    Publication date: June 14, 2012
    Applicant: NVIDIA CORPORATION
    Inventors: Zheng Yu Zheng, Oren Rubinstein, Yudong Tan, Saket Arun Jamkar, Yogesh Kulkarni
  • Publication number: 20110291748
    Abstract: Power management systems and methods that facilitate efficient and effective power conservation are presented. In one embodiment a power management method comprises: performing an initiation metric determination process, and adjusting operations of a logic component based on said threshold value. In one exemplary implementation, the initiation metric determination process includes monitoring activity of a logic component, and establishing a power conservation initiation threshold value. The initiation metric determination process can include performing a system architecture characteristic analysis in which a system architecture power-consumption break-even time (BE) is determined for the system. The initiation metric determination process can also include performing a system utilization analysis process is performed in which idle period durations detected during said monitoring are sorted into a variety of different length intervals and analyzed accordingly.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 1, 2011
    Applicant: NVIDIA CORPORATION
    Inventors: Sau Yan Keith Li, Thomas Edward Dewey, Saket Arun Jamkar, Amit Parikh