Abstract: A method includes transferring a first subset of the first LEDs from a first substrate to a first backplane to form first subpixels in pixel regions, transferring a first subset of the second LEDs to a second backplane and separating the first subset of the second LEDs from a second substrate to leave first vacancies on the second substrate, forming an additional electrically conductive material on a second subset of second LEDs located on the second substrate after transferring the first subset of the second LEDs to the second backplane, positioning the second substrate over the first backplane, such that the first subpixels are disposed in the first vacancies, and transferring the second subset of the second LEDs to a second subset of bonding structures on the first backplane to form second subpixels in the pixel regions, while a gap exists between the first subpixels and the second substrate.

Abstract: A method of forming light emitting diodes includes forming a first-conductivity-type compound semiconductor layer over a substrate, etching the first-conductivity-type compound semiconductor layer to form a first pillar structure and a second pillar structure without exposing the substrate between the first and the second pillar structures, selectively growing a semiconductor active layer over the first and the second pillar structures, and selectively growing a second-conductivity-type compound semiconductor layer on the semiconductor active layer.

Abstract: A light emitting device includes a first optical cavity bounded by cavity walls, a first light emitting diode located in the first optical cavity and configured to emit blue or ultraviolet radiation first incident photons, a first color conversion material located over the first light emitting diode and configured to absorb the first incident photons emitted by the light emitting diode and to generate first converted photons having a longer peak wavelength than a peak wavelength of the first incident photons, and a first color selector located over the first color conversion material and configured to absorb or reflect the first incident photons and to transmit the first converted photons.

Abstract: A method of forming a light emitting device includes forming a first doped compound semiconductor layer over a substrate, forming an active layer over the first doped compound semiconductor layer, forming a second doped compound semiconductor layer over the active layer, forming a patterned ion implantation mask layer, and implanting ions of at least one electrically inactive dopant species in portions of the active layer that are not masked by the patterned ion implantation mask layer. An electrically inactive insulating region including a semiconductor material and atoms of the at least one electrically inactive dopant species is formed. Unimplanted portions of the active layer constitute active regions of an array of light emitting diodes.

Abstract: A light emitting diode includes a mesa structure containing a first-conductivity-type compound semiconductor layer, an active layer stack configured to emit light at a peak wavelength, and a second-conductivity-type compound semiconductor layer, and a passivation material layer contacting at least a sidewall of the mesa structure. The passivation material layer has a first crystal structure that matches a second crystal structure of the first-conductivity-type compound semiconductor layer and the second-conductivity-type compound semiconductor layer.

Abstract: A light-emitting device includes a backplane, light-emitting diodes (LEDs) located over a front side of the backplane, and microlenses respectively disposed over the LEDs. Each microlens includes a back surface having a first surface area and configured to receive light emitted from a corresponding LED, an opposing front surface having a second surface area and configured to emit the received light, and at least one sidewall extending from the front surface to the back surface. The second surface area is greater than the first surface area.

Abstract: A method includes transferring a first subset of the first LEDs from a first substrate to a first backplane to form first subpixels in pixel regions, transferring a first subset of the second LEDs to a second backplane and separating the first subset of the second LEDs from a second substrate to leave first vacancies on the second substrate, forming an additional electrically conductive material on a second subset of second LEDs located on the second substrate after transferring the first subset of the second LEDs to the second backplane, positioning the second substrate over the first backplane, such that the first subpixels are disposed in the first vacancies, and transferring the second subset of the second LEDs to a second subset of bonding structures on the first backplane to form second subpixels in the pixel regions, while a gap exists between the first subpixels and the second substrate.

Abstract: A structure includes a first material layer, a second material layer, and a stress relaxation layer having a thickness of 0.5 nm or less between the first material layer and the second material layer.

Abstract: A structure includes a first material layer, a second material layer, and a dielectric masking layer having a thickness of 20 nm or less and containing pinholes having a width of 200 nm or less filled with the second material of second material layer located between the first material layer and the second material layer. A method of forming a LED includes forming a buffer layer over a support substrate, forming a dielectric masking layer having a thickness of 20 nm or less and containing pinholes having a width of 200 nm or less on the semiconductor buffer layer, forming a n-doped semiconductor material layer on the dielectric masking layer such that the n-doped semiconductor material of the n-doped semiconductor layer fills the pinholes and contacts the buffer layer, forming an active region over the n-doped semiconductor material layer, and forming a p-doped semiconductor material layer over the active region.

Abstract: Methods for reliable interconnect structures between thin metal capture pads and TGV metallization and resulting devices are provided. Embodiments include forming a TGV in a glass substrate; filling with metal conductive paste; forming a metal layer on top and bottom surfaces of the substrate; patterning the metal layer, leaving at least a portion over the TGV top surface and an area surrounding the TGV; forming a dielectric layer on the metal layer and on the substrate top and bottom surfaces; patterning the dielectric layer, including exposing the metal layer over the TGV top surface and the area surrounding the TGV; forming a second metal layer on the dielectric layer and on the exposed portion of the first metal layer over the TGV top surface and the area surrounding the TGV; patterning the second metal layer exposing the dielectric layer; and forming a third metal layer on the second metal layer.

Abstract: A methodology for a thin, flexible substrate having integrated passive circuit elements, and the resulting device are disclosed. Embodiments may include integrating one or more passive circuit components on a first or second surface of a substrate, and interconnecting one or more integrated circuit (IC) dies on a second surface of the interposer to the one or more passive circuit components with one or more metal-filled vias between the first and second surfaces, the first and second surfaces being opposite surfaces of the substrate.

Abstract: A methodology for a thin, flexible substrate having integrated passive circuit elements, and the resulting device are disclosed. Embodiments may include integrating one or more passive circuit components on a first or second surface of a substrate, and interconnecting one or more integrated circuit (IC) dies on a second surface of the interposer to the one or more passive circuit components with one or more metal-filled vias between the first and second surfaces, the first and second surfaces being opposite surfaces of the substrate.

Abstract: A methodology for a thin, flexible substrate having integrated passive circuit elements, and the resulting device are disclosed. Embodiments may include integrating one or more passive circuit components on a first or second surface of a substrate, and interconnecting one or more integrated circuit (IC) dies on a second surface of the interposer to the one or more passive circuit components with one or more metal-filled vias between the first and second surfaces, the first and second surfaces being opposite surfaces of the substrate.

Abstract: An electrochemical planarization apparatus for planarizing a metallized surface on a workpiece includes a polishing pad and a platen. The platen is formed of conductive material, is disposed proximate to the polishing pad and is configured to have a negative charge during at least a portion of a planarization process. At least one electrical conductor is positioned within the platen. The electrical conductor has a first end connected to a power source. A workpiece carrier is configured to carry a workpiece and press the workpiece against the polishing pad. The power source applies a positive charge to the workpiece via the electrical conductor so that an electric potential difference between the metallized surface of the workpiece and the platen is created to remove at least a portion of the metallized surface from the workpiece.

Abstract: This invention describes a method of making solar cells wherein the efficiency of the solar cell is enhanced by defining a diffraction grating either on top of the cell or at the bottom of the cell. The diffraction grating spacing is defined such that it bends one or more wavelengths of the incident radiation thereby making those wavelengths traverse in the direction of the plane of the device. The addition of a diffraction grating is done in conjunction with thinning down the cell such that the minority carriers generated (holes and electrons) have a higher probability of being collected. The combined effect of the diffraction grating and the reduced thickness in the solar cell increases the efficiency of the solar cell.

Abstract: An apparatus for planarizing a workpiece has a web with a face which is positioned adjacent the workpiece during planarization. At least one tension assembly is configured to maintain tension of the web. An orbiting assembly is configured to orbit the web relative to the workpiece. The apparatus for planarizing a workpiece may include first and second polishing surfaces where the first polishing surface has a substantially horizontal web with a face which is positioned adjacent the workpiece during the planarization process. The apparatus may also have a rotatable carousel and at least two workpiece carriers suspended from the carousel. Each of the carriers is configured to carry a workpiece and press the workpiece against one of the polishing surfaces while causing relative motion between the workpiece and the polishing surface. An apparatus for planarizing a workpiece which includes a plurality of polishing stations is also disclosed.

Abstract: The invention includes components comprising an alloy containing a base metal and less than or equal to 30% alloying elements. The material has a grain size of less than or equal to about 30 microns and an absence of voids and inclusions of a size greater than 1 micron. The components have a yield strength at least 50% greater than the identical alloy composition in the 0 temper condition. Where the material is heat treatable, the yield strength is at least 10% greater than the identical composition in the T6 temper condition. The invention includes a method of producing components by casting and initial treatment to form a billet. The billet is subjected to equal channel angular extrusion and subsequent annealing at a temperature of less than or equal to 0.85 times the minimum temperature for inducing growth of submicron grains to over 1 micron.

Abstract: A method for polishing a metal layer on a workpiece is provided wherein relative motion is produced between the metal layer and a polishing surface and wherein the metal layer has a polish resistant film thereon. The metal layer is first pre-treated to substantially remove the polish resistant film. Next, the metal layer is polished at low pressure between the metal layer and the polishing surface in the presence of a polishing solution. The pretreating may be accomplished by, for example, sputtering, polishing the polish-resistant film in the presence of abrasive polishing solution, polishing the polish-resistant film at higher pressures between the film and the polishing surface, maintaining the temperature of the pretreating step to be substantially between 10 degrees Centigrade and 30 degrees Centigrade, and chemically removing the film.

Abstract: A multi-process workpiece apparatus is disclosed. The multi-process workpiece apparatus includes an electrochemical deposition apparatus which has a wafer contacting surface having at least one electrical conductor disposed therein. The multi-process workpiece apparatus also includes a planarization apparatus and at least one workpiece handling robot configured to transport a workpiece from the electrochemical deposition apparatus to the planarization apparatus.

Abstract: An electrochemical planarization apparatus for planarizing a metallized surface on a workpiece includes a polishing pad and a platen. The platen is formed of conductive material, is disposed proximate to the polishing pad and is configured to have a negative charge during at least a portion of a planarization process. At least one electrical conductor is positioned within the platen. The electrical conductor has a first end connected to a power source. A workpiece carrier is configured to carry a workpiece and press the workpiece against the polishing pad. The power source applies a positive charge to the workpiece via the electrical conductor so that an electric potential difference between the metallized surface of the workpiece and the platen is created to remove at least a portion of the metallized surface from the workpiece.