Patents by Inventor Saket Jalan
Saket Jalan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11740968Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.Type: GrantFiled: May 25, 2022Date of Patent: August 29, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Saket Jalan, Indu Prathapan, Abhishek Ganapati Karkisaval
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Patent number: 11631454Abstract: In described examples, an apparatus includes: a set of control registers containing control bits for controlling circuitry coupled to receive register write enable signals and to receive input data; a memory for storing data corresponding to the control bits coupled to receive an address and a memory write enable signal; decode circuitry coupled to output the register write enable signals; a data output bus coupled to receive data from the memory but free from connections to the control registers; and a controller coupled to receive an address, coupled to output the address on an internal address bus, coupled to output a register write enable signal, and coupled to output the memory write enable signal, configured to cause data to be written to a selected control register corresponding to the address received, and to cause the data to be contemporaneously stored at a memory location corresponding to the address received.Type: GrantFiled: January 16, 2020Date of Patent: April 18, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Saket Jalan, Sudesh Chandra Srivastava, Mohammed Nabeel
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Patent number: 11538069Abstract: A social networking system associates identification information with combinations of values used to generate a dynamically-created advertisement. Interactions with the dynamically-created advertisement by social networking system users are also associated with the dynamically-created advertisement. The social networking system uses the identification information to present the same combination of values used to generate the dynamically-created advertisement to additional social networking system users. Additionally, information describing interactions with the dynamically-created advertisement is determined from the interactions associated with the identification information, allowing the dynamically-created advertisement to be included in a personalized feed of content items presented to an additional user along with information describing interactions by various users presented with the same combination of values of components in the dynamically-created advertisement.Type: GrantFiled: September 6, 2019Date of Patent: December 27, 2022Assignee: Meta Platforms, Inc.Inventors: Scott Aaron Shapiro, Shreehari Manikarnika, Brian M. Wrightson, Saket Jalan, Gang Wu
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Publication number: 20220283899Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.Type: ApplicationFiled: May 25, 2022Publication date: September 8, 2022Inventors: Saket Jalan, Indu Prathapan, Abhishek Ganapati Karkisaval
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Patent number: 11372715Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.Type: GrantFiled: February 13, 2020Date of Patent: June 28, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Saket Jalan, Indu Prathapan, Abhishek Ganapati Karkisaval
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Patent number: 11320488Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.Type: GrantFiled: January 28, 2021Date of Patent: May 3, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sundarrajan Rangachari, Saket Jalan
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Patent number: 11194944Abstract: A method that includes disabling circuit paths in a circuit under test during transition fault testing (TFT) of valid timing paths of the circuit under test. The method then tests the circuit paths at slower clock speeds than the clock speed of the valid timing paths during TFT of the circuit paths. Finally, the method tests the circuit paths and the valid timing paths to facilitate testing of the circuit under test.Type: GrantFiled: August 11, 2020Date of Patent: December 7, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Wilson Pradeep, Prakash Narayanan, Saket Jalan
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Publication number: 20210148976Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.Type: ApplicationFiled: January 28, 2021Publication date: May 20, 2021Inventors: Sundarrajan Rangachari, Saket Jalan
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Patent number: 10935602Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.Type: GrantFiled: May 7, 2018Date of Patent: March 2, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sundarrajan Rangachari, Saket Jalan
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Publication number: 20200372197Abstract: A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.Type: ApplicationFiled: August 11, 2020Publication date: November 26, 2020Inventors: WILSON PRADEEP, PRAKASH NARAYANAN, SAKET JALAN
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Patent number: 10838808Abstract: In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.Type: GrantFiled: June 26, 2019Date of Patent: November 17, 2020Assignee: Texas Instruments IncorporatedInventors: Indu Prathapan, Prashanth Saraf, Desmond Pravin Martin Fernandes, Saket Jalan
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Patent number: 10776546Abstract: A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.Type: GrantFiled: May 13, 2019Date of Patent: September 15, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Wilson Pradeep, Prakash Narayanan, Saket Jalan
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Publication number: 20200210287Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.Type: ApplicationFiled: February 13, 2020Publication date: July 2, 2020Inventors: Saket Jalan, Indu Prathapan, Abhishek Ganapati Karkisaval
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Publication number: 20200152261Abstract: In described examples, an apparatus includes: a set of control registers containing control bits for controlling circuitry coupled to receive register write enable signals and to receive input data; a memory for storing data corresponding to the control bits coupled to receive an address and a memory write enable signal; decode circuitry coupled to output the register write enable signals; a data output bus coupled to receive data from the memory but free from connections to the control registers; and a controller coupled to receive an address, coupled to output the address on an internal address bus, coupled to output a register write enable signal, and coupled to output the memory write enable signal, configured to cause data to be written to a selected control register corresponding to the address received, and to cause the data to be contemporaneously stored at a memory location corresponding to the address received.Type: ApplicationFiled: January 16, 2020Publication date: May 14, 2020Inventors: Saket Jalan, Sudesh Chandra Srivastava, Mohammed Nabeel
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Patent number: 10599514Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.Type: GrantFiled: December 15, 2017Date of Patent: March 24, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Saket Jalan, Indu Prathapan, Abishek Ganapati Karkisaval
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Patent number: 10559351Abstract: In described examples, an apparatus includes: a set of control registers containing control bits for controlling circuitry coupled to receive register write enable signals and to receive input data; a memory for storing data corresponding to the control bits coupled to receive an address and a memory write enable signal; decode circuitry coupled to output the register write enable signals; a data output bus coupled to receive data from the memory but free from connections to the control registers; and a controller coupled to receive an address, coupled to output the address on an internal address bus, coupled to output a register write enable signal, and coupled to output the memory write enable signal, configured to cause data to be written to a selected control register corresponding to the address received, and to cause the data to be contemporaneously stored at a memory location corresponding to the address received.Type: GrantFiled: February 20, 2017Date of Patent: February 11, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Saket Jalan, Sudesh Chandra Srivastava, Mohammed Nabeel
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Publication number: 20190317855Abstract: In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.Type: ApplicationFiled: June 26, 2019Publication date: October 17, 2019Inventors: Indu Prathapan, Prashanth Saraf, Desmond Pravin Martin Fernandes, Saket Jalan
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Patent number: 10445785Abstract: A social networking system associates identification information with combinations of values used to generate a dynamically-created advertisement. Interactions with the dynamically-created advertisement by social networking system users are also associated with the dynamically-created advertisement. The social networking system uses the identification information to present the same combination of values used to generate the dynamically-created advertisement to additional social networking system users. Additionally, information describing interactions with the dynamically-created advertisement is determined from the interactions associated with the identification information, allowing the dynamically-created advertisement to be included in a personalized feed of content items presented to an additional user along with information describing interactions by various users presented with the same combination of values of components in the dynamically-created advertisement.Type: GrantFiled: November 21, 2013Date of Patent: October 15, 2019Assignee: Facebook, Inc.Inventors: Scott Aaron Shapiro, Shreehari Manikarnika, Brian M. Wrightson, Saket Jalan, Gang Wu
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Publication number: 20190266303Abstract: A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.Type: ApplicationFiled: May 13, 2019Publication date: August 29, 2019Inventors: WILSON PRADEEP, PRAKASH NARAYANAN, SAKET JALAN
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Patent number: 10372531Abstract: In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.Type: GrantFiled: July 19, 2017Date of Patent: August 6, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Indu Prathapan, Prashanth Saraf, Desmond Pravin Martin Fernandes, Saket Jalan