Abstract: A PCI host bridge (PHB) includes a warm reset mode and a full reset mode. When a fatal error occurs, the type of fatal error is determined, a reset mode corresponding to that type of fatal error is determined, and a reset corresponding to the reset mode is performed. A full reset clears the error registers, status registers and configuration registers, which then requires the configuration registers to be reconfigured before the PHB can be reinitialized. A warm reset clears the error registers and status registers, but does not clear the configuration registers. A warm reset thus does not require the time to write to the configuration registers, and the PHB can be reinitialized using the existing configuration data in the configuration registers while link training is done in parallel. When initialization of the PHB after a warm reset is not successful, a full reset is performed.

Abstract: A PCI host bridge (PHB) includes a warm reset mode and a full reset mode. When a fatal error occurs, the type of fatal error is determined, a reset mode corresponding to that type of fatal error is determined, and a reset corresponding to the reset mode is performed. A full reset clears the error registers, status registers and configuration registers, which then requires the configuration registers to be reconfigured before the PHB can be reinitialized. A warm reset clears the error registers and status registers, but does not clear the configuration registers. A warm reset thus does not require the time to write to the configuration registers, and the PHB can be reinitialized using the existing configuration data in the configuration registers while link training is done in parallel. When initialization of the PHB after a warm reset is not successful, a full reset is performed.

Abstract: A PCI host bridge (PHB) includes a warm reset mode and a full reset mode. When a fatal error occurs, the type of fatal error is determined, a reset mode corresponding to that type of fatal error is determined, and a reset corresponding to the reset mode is performed. A full reset clears the error registers, status registers and configuration registers, which then requires the configuration registers to be reconfigured before the PHB can be reinitialized. A warm reset clears the error registers and status registers, but does not clear the configuration registers. A warm reset thus does not require the time to write to the configuration registers, and the PHB can be reinitialized using the existing configuration data in the configuration registers while link training is done in parallel. When initialization of the PHB after a warm reset is not successful, a full reset is performed.

Abstract: A system can translate an input/output (I/O) direct memory access (DMA) address to a physical system memory address in a data processing system. In response to receiving a DMA packet containing a requester identity (RID) associated with a partitionable endpoint (PE) number and an I/O DMA address, the system can retrieve an entry associated with the RID from a first translation validation table (TVT). Using that entry, the system can validate the number of TVT entries and extract from the I/O DMA address an offset. This offset can be validated and used to retrieve an entry in a second TVT. Data from this entry can be validated and the system can use this to access another table to retrieve the translation to the physical system memory address.

Abstract: A method, system and computer program product are provided for implementing dynamic altering of a Single Root Input/Output Virtualization (SRIOV) virtual function (VF) resources including direct memory access (DMA) windows without bringing down the VF in a virtualized system. A request to alter VF resources is received, such as a dynamic request based on usage statistics or change in need of the user. Pending DMA requests are completed for the VF resources to be altered. Responsive to completing the DMA requests, new buffers are allocated for the resized DMA windows without bringing down the VF in a virtualized system.

Abstract: A PCI host bridge (PHB) includes a warm reset mode and a full reset mode. When a fatal error occurs, the type of fatal error is determined, a reset mode corresponding to that type of fatal error is determined, and a reset corresponding to the reset mode is performed. A full reset clears the error registers, status registers and configuration registers, which then requires the configuration registers to be reconfigured before the PHB can be reinitialized. A warm reset clears the error registers and status registers, but does not clear the configuration registers. A warm reset thus does not require the time to write to the configuration registers, and the PHB can be reinitialized using the existing configuration data in the configuration registers while link training is done in parallel. When initialization of the PHB after a warm reset is not successful, a full reset is performed.

Abstract: A PCI host bridge (PHB) includes a warm reset mode and a full reset mode. When a fatal error occurs, the type of fatal error is determined, a reset mode corresponding to that type of fatal error is determined, and a reset corresponding to the reset mode is performed. A full reset clears the error registers, status registers and configuration registers, which then requires the configuration registers to be reconfigured before the PHB can be reinitialized. A warm reset clears the error registers and status registers, but does not clear the configuration registers. A warm reset thus does not require the time to write to the configuration registers, and the PHB can be reinitialized using the existing configuration data in the configuration registers while link training is done in parallel. When initialization of the PHB after a warm reset is not successful, a full reset is performed.

Abstract: A PCI host bridge (PHB) includes a warm reset mode and a full reset mode. When a fatal error occurs, the type of fatal error is determined, a reset mode corresponding to that type of fatal error is determined, and a reset corresponding to the reset mode is performed. A full reset clears the error registers, status registers and configuration registers, which then requires the configuration registers to be reconfigured before the PHB can be reinitialized. A warm reset clears the error registers and status registers, but does not clear the configuration registers. A warm reset thus does not require the time to write to the configuration registers, and the PHB can be reinitialized using the existing configuration data in the configuration registers while link training is done in parallel. When initialization of the PHB after a warm reset is not successful, a full reset is performed.

Abstract: A method, system and computer program product are provided for implementing dynamic altering of a Single Root Input/Output Virtualization (SRIOV) virtual function (VF) resources including direct memory access (DMA) windows without bringing down the VF in a virtualized system. A request to alter VF resources is received, such as a dynamic request based on usage statistics or change in need of the user. Pending DMA requests are completed for the VF resources to be altered. Responsive to completing the DMA requests, new buffers are allocated for the resized DMA windows without bringing down the VF in a virtualized system.

Abstract: An I/O DMA address may be translated for a flexible number of entries in a translation validation table (TVT) for a partitionable endpoint number, when a particular entry in the TVT is accessed based on the partitionable endpoint number. A presence of an extended mode bit can be detected in a particular TVT entry. Based on the presence of the extended mode bit, an entry in the extended TVT can be accessed and used to translate the I/O DMA address to a physical address.

Abstract: An I/O DMA address may be translated for a flexible number of entries in a translation validation table (TVT) for a partitionable endpoint number, when a particular entry in the TVT is accessed based on the partitionable endpoint number. A presence of an extended mode bit can be detected in a particular TVT entry. Based on the presence of the extended mode bit, an entry in the extended TVT can be accessed and used to translate the I/O DMA address to a physical address.

Abstract: A PCI host bridge (PHB) includes a warm reset mode and a full reset mode. When a fatal error occurs, the type of fatal error is determined, a reset mode corresponding to that type of fatal error is determined, and a reset corresponding to the reset mode is performed. A full reset clears the error registers, status registers and configuration registers, which then requires the configuration registers to be reconfigured before the PHB can be reinitialized. A warm reset clears the error registers and status registers, but does not clear the configuration registers. A warm reset thus does not require the time to write to the configuration registers, and the PHB can be reinitialized using the existing configuration data in the configuration registers while link training is done in parallel. When initialization of the PHB after a warm reset is not successful, a full reset is performed.

Abstract: A PCI host bridge (PHB) includes a warm reset mode and a full reset mode. When a fatal error occurs, the type of fatal error is determined, a reset mode corresponding to that type of fatal error is determined, and a reset corresponding to the reset mode is performed. A full reset clears the error registers, status registers and configuration registers, which then requires the configuration registers to be reconfigured before the PHB can be reinitialized. A warm reset clears the error registers and status registers, but does not clear the configuration registers. A warm reset thus does not require the time to write to the configuration registers, and the PHB can be reinitialized using the existing configuration data in the configuration registers while link training is done in parallel. When initialization of the PHB after a warm reset is not successful, a full reset is performed.

Abstract: An I/O DMA address may be translated for a flexible number of entries in a translation validation table (TVT) for a partitionable endpoint number, when a particular entry in the TVT is accessed based on the partitionable endpoint number. A presence of an extended mode bit can be detected in a particular TVT entry. Based on the presence of the extended mode bit, an entry in the extended TVT can be accessed and used to translate the I/O DMA address to a physical address.

Abstract: An I/O DMA address may be translated for a flexible number of entries in a translation validation table (TVT) for a partitionable endpoint number, when a particular entry in the TVT is accessed based on the partitionable endpoint number. A presence of an extended mode bit can be detected in a particular TVT entry. Based on the presence of the extended mode bit, an entry in the extended TVT can be accessed and used to translate the I/O DMA address to a physical address.

Abstract: A system can translate an input/output (I/O) direct memory access (DMA) address to a physical system memory address in a data processing system. In response to receiving a DMA packet containing a requester identity (RID) associated with a partitionable endpoint (PE) number and an I/O DMA address, the system can retrieve an entry associated with the RID from a first translation validation table (TVT). Using that entry, the system can validate the number of TVT entries and extract from the I/O DMA address an offset. This offset can be validated and used to retrieve an entry in a second TVT. Data from this entry can be validated and the system can use this to access another table to retrieve the translation to the physical system memory address.