Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Abstract: A computer-implemented method of locking-in investment gains can include initializing an investment fund having a net asset value per share. The investment fund can include assets allocated to at least a discount instrument and a derivative instrument, where the discount instrument provides a floor value of the net asset value per share. The method can further include selecting a target value for the investment fund. In addition, in some instances, the method can include reinitializing the investment fund in response to one or more of the following: (a) the investment fund at least achieving the target value and (b) expiration of an investment period of the investment fund. Reinitializing the investment fund can include rolling over the assets of the investment fund.

Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Abstract: An oscillator that can be used within a high voltage generation and regulation system for non-volatile memory. The system may comprise a charge pump that may have at least one pump and an oscillator. In one aspect the oscillator provides clock signals to the pump. The output of the oscillator may be disabled without turning off the clock generation. The oscillator may be a ring oscillator. In one aspect, the ring oscillator and the output stage may comprise inverters with a capacitor coupled to the output of the inverter. In one aspect, the ratio of the capacitors in the ring oscillator to the capacitor in the output stage determine the phase shift between the two clock signals. In another aspect, the capacitance of the capacitors are identical and a bias applied the ring oscillator and the output stage are radioed to adjust the phase between the two clock signals.

Abstract: An operational amplifier comprises multiple stages. A differential input stage that includes an adaptive high voltage differential pair generates up and down output currents in response to up and down input voltages. The differential input stage includes adaptive common input high voltage (HV) bias. An intermediate stage converts the up and down output currents into a first output voltage signal. The intermediate stage includes a folded cascode arrangement. The intermediate stage is biased by fixed voltage bias signals. The intermediate stage also includes unaffected slew rate stability compensation and a combined split stability compensation. An output stage includes a class AB source follower driver that generates a second output voltage signal in response to the first output voltage signal. The output stage is biased with an adaptive push-pull source follower output HV bias. The output stage includes feed-forward slew rate enhancement.

Abstract: Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.

Abstract: A digital multilevel bit memory array system comprises regular memory arrays and redundant memory arrays. A regular y-driver corresponds to each memory array to read or write contents to a multilevel bit memory cell and compare the read cell content to reference voltage levels to determine the data stored in the corresponding memory cell. Likewise, similar functions are performed by the redundant y-driver circuit for the redundant memory array. During the verification of the contents of the memory cell, if the read voltage is outside a certain margin requirement for a level of the reference voltage, a signal is generated in real time so that data from the bad y-driver is not output and data from the redundant y-driver corresponding to the redundant memory array is read out. The memory array system may also include a fractional multilevel redundancy.

Abstract: A high voltage generator provides high voltage signals with different regulated voltage levels. A charge pump generates the high voltage, and includes a quadrature phase forward and backward Vt-canceling high-voltage self-biasing charge pump with a powerup-assist diode. A high voltage series regulator generates the high voltage supply levels, and includes slew rate enhancement and trimmable diode regulation. A nested loop regulator eliminates shunt regulation.

Abstract: A high voltage generator provides high voltage signals with different regulated voltage levels. A charge pump generates the high voltage, and includes a quadrature phase forward and backward Vt-canceling high-voltage self-biasing charge pump with a powerup-assist diode. A high voltage series regulator generates the high voltage supply levels, and includes slew rate enhancement and trimmable diode regulation. A nested loop regulator eliminates shunt regulation.

Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Abstract: Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.

Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.