Patents by Inventor Sakutaro Sato

Sakutaro Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060212749
    Abstract: A communication method for detecting failure and for performing immediate stop processing is provided. It is a failure communication method of a computer, comprising a plurality of units A, separated by partitions, and a unit B interconnecting the units A, in which the unit B broadcasts identical information, generated based on information transferred from the units A to the unit B, to the units A, wherein when failure occurs in a unit A, the unit B is notified of failure information, receives the failure information, generates identical failure information based on the failure information and notifies the units A in normal conditions of the identical failure information, and the units A receive the identical failure information, if it is from a unit A belonging to the same partition, operation of the units A belonging to the same partition is s topped immediately, and otherwise operation of the units A is continued.
    Type: Application
    Filed: September 29, 2005
    Publication date: September 21, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Shigeru Kawahara, Takayuki Kinoshita, Shintaro Itozawa, Koji Hosoe, Sakutaro Sato
  • Patent number: 5737373
    Abstract: Provision is made of a phase-locked loop circuit including a voltage-controlled oscillator, a phase comparator, and a low-pass filter, a pulse-cancelling processing unit, a pulse-cancelling control unit, and a divider circuit. By dividing the pulse-cancelling request signal of the pointer-action into several bits by the divider circuit, the pulse-cancelling control unit gradually changes the input phase to the phase comparator or the control voltage to the voltage-controlled oscillator in several stages from the state before the 1-bit pulse-cancelling to the state of the 1-bit pulse-cancelling so that the phase of the output clock signal from the voltage-controlled oscillator matches the 1-bit pulse-cancelled input clock signal. By this, phase control of the output clock signal is performed in units of less than 1-bit and jitter is suppressed.
    Type: Grant
    Filed: October 11, 1994
    Date of Patent: April 7, 1998
    Assignee: Fujitsu Limited
    Inventors: Sakutaro Sato, Naonobu Fujimoto
  • Patent number: 5406255
    Abstract: A communication system comprising at least one working system for receiving a signal from a source, at least one protection system for receiving the signal from the source, a detection part for detecting an alarm state of the signals received via the working system and the protection system and for outputting an alarm signal if the alarm state is detected in at least one of the working system and the protection system, a switching part for selectively outputting the signal received via one of the working system and the protection system in response to a control signal which determines a connection of the switching part, and a control part for supplying the control signal to the switching part based on the alarm signals from the detection part. The control part disregards the alarm signals if the alarm signals are generated from the detection part with respect to the working system and the protection signal approximately at the same time.
    Type: Grant
    Filed: October 27, 1992
    Date of Patent: April 11, 1995
    Assignee: Fujitsu Limited
    Inventors: Naonobu Fujimoto, Sakutaro Sato
  • Patent number: 5122677
    Abstract: A clock switching apparatus includes a first phase synchronizing part for receiving n (n is an integer) input clock signals and for generating n first clock signals respectively related to the n input clock signals. Each of the n first clock signals has a frequency higher than that of a corresponding one of the n input clock signals. A selector selects one of the n first clock signals. A frequency divider generates a second clock signal obtained by frequency-dividing the one of the n first clock signals selected by the selector. A second phase synchronizing part generates an output clock signal synchronized with the second clock signal.
    Type: Grant
    Filed: September 3, 1991
    Date of Patent: June 16, 1992
    Assignee: Fujitsu Limited
    Inventor: Sakutaro Sato