Patents by Inventor Sakyun Hwang

Sakyun Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7092466
    Abstract: A deserializer that deserializes a high data rate bit stream to extract a set of bits contained therein includes a data sampler, a serial-to-parallel converter, a windowing block, and a phase error detection block. The data sampler over samples the high data rate bit stream to produce a serial group of samples corresponding to the set of bits of the high data rate bit stream. The serial-to-parallel converter couples to the data sampler and converts the serial group of samples into a parallel group of samples. The windowing block receives the parallel group of samples and produces output bits corresponding to the set of bits. The phase error detection block couples to the windowing block, detects errors in the alignment of the overlapping sampling windows of the windowing block, and directs the windowing block to adjust the operation. The phase error detection block and the windowing block compensate for bit stream jitter and intersymbol interference.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: August 15, 2006
    Assignee: Broadcom Corporation
    Inventors: Sakyun Hwang, Seong-Ho Lee, Christopher R. Pasqualino, Stephen G. Petilli, Hao O. Phung
  • Publication number: 20030115542
    Abstract: A deserializer that deserializes a high data rate bit stream to extract a set of bits contained therein includes a data sampler, a serial-to-parallel converter, a windowing block, and a phase error detection block. The data sampler over samples the high data rate bit stream to produce a serial group of samples corresponding to the set of bits of the high data rate bit stream. The serial-to-parallel converter couples to the data sampler and converts the serial group of samples into a parallel group of samples. The windowing block receives the parallel group of samples and produces output buts corresponding to the set of bits. The phase error detection block couples to the windowing block, detects errors in the alignment of the overlapping sampling windows of the windowing block, and directs the windowing block to adjust the operation. The phase error detection block and the windowing block compensate for bits stream jitter and intersymbol interference.
    Type: Application
    Filed: May 13, 2002
    Publication date: June 19, 2003
    Inventors: Sakyun Hwang, Seong-Ho Lee, Christopher R. Pasqualino, Stephen G. Petilli, Hao O. Phung