Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. The epitaxial monocrystalline material has an upper surface that is positioned coplanar with a surface of an adjacent layer carried by the substrate, thereby facilitating the fabrication of overlying layers that bridge the epitaxial monocrystalline material and the adjacent layer.

Abstract: A fusible link is fabricated using sidewall spacer technology. The fusible link of the present requires low fusing power because a fusible link having a small cross-sectional area is obtainable. A conductive or semiconductive, fusible sidewall spacer is formed around a platform or in a well of a dielectric layer. Each fusible link may have two fusible portions per site, resulting in a built-in redundancy. Alternatively, the packing density of the fusible links may be increased by using each side of the fusible sidewall spacer as a fusible link. This process is compatible with bipolar and BICMOS processes used in fabricating high performance memory devices.

Abstract: An improved means and method for forming an optical sensor within an integrated circuit structure is described. An epi-coated semiconductor wafer is masked and a cavity etched through the epi-layer to the underlying substrate. A dielectric sidewall is formed on the cavity sidewall and a substantially intrinsic semiconductor region, preferably grown by selective epitaxy, to refill the cavity. The upper surface of the intrinsic region is then heavily doped and contacted by a low resistance polysilicon layer which is substantially transparent to incoming light. The method forms a high sensitivity PIN photo-sensor having a thick space-charge region for efficient capture of the hole-electron pairs produced by the incoming light. The fabrication techniques are compatible with the processing requirements for other integrated circuit devices formed on the same chip and to which the PIN device is coupled without wire bonds, tabs, bumps or the like.

Abstract: An improved means and method for forming an optical sensor within an integrated circuit structure is described. An epi-coated semiconductor wafer is masked and a cavity etched through the epi-layer to the underlying substrate. A dielectric sidewall is formed on the cavity sidewall and a substantially intrinsic semiconductor region, preferably grown by selective epitaxy, to refill the cavity. The upper surface of the intrinsic region is then heavily doped and contacted by a low resistance polysilicon layer which is substantially transparent to incoming light. The method forms a high sensitivity PIN photo-sensor having a thick space-charge region for efficient capture of the hole-electron pairs produced by the incoming light. The fabrication techniques are compatible with the processing requirements for other integrated circuit devices formed on the same chip and to which the PIN device is coupled without wire bonds, tabs, bumps or the like.

Abstract: A method for fabricating self-aligned, walled emitter, oxide isolated integrated circuits. A layer of oxidation resistant material is formed on an oxide isolated epitaxial layer on a silicon substrate. A pattern of apertures is opened in the oxidation resistant layer to expose portions of the epitaxial layer. The apertures extend across the oxide isolated silicon material and define the spaces between the contacts of the active devices of the circuit. Dopant impurities are applied through these apertures to form an inactive base region. The substrate is heated in an oxidizing ambient to form a relatively thick oxide on a portion of the epitaxial layer exposed through the apertures. The oxidation resistant layer is again selectively etched to expose those portions of the epitaxial layer where the active device regions are to be formed. In this step a single mask is used to open a plurality of device regions.

Abstract: A double master mask process for fabricating semiconductor integrated circuits is provided in which selectively etchable dielectric layers and ion implanted resistors are used to form dense integrated circuits with a minimum number of critical alignments. A first silicon dioxide silicon nitride layer used in conjunction with a first master photomask defines a base region and an isolation region which are self-aligned with respect to each other and with respect to resistor contact regions. After isolation and base diffusion, the first oxide/nitride layer is stripped away and a second oxide/nitride layer is grown. Using a photoresist mask, a predeposition layer for the resistor is then formed using ion implantation through the oxide/nitride layers. A second master photomask allows the formation of collector and emitter regions and base and resistor contact which are self-aligned with respect to each other.