Patents by Inventor Salah M. Werfelli
Salah M. Werfelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230153547Abstract: The present invention relates to a system for accurate video speech translation and synchronisation. The present invention particularly related to a system for accurate video speech translation and synchronisation with the duration of the speech. The present invention discloses a system to minimise the inaccuracy in the translation and also synchronise the translated speech with the duration of audio and video elements.Type: ApplicationFiled: November 12, 2021Publication date: May 18, 2023Inventors: SALAH M. WERFELLI, SAM L. APPLETON, KHALED JASSIM J. S. AL-JABER, TANWIR ZAFAR SYEDMOHAMMAD
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Publication number: 20230156047Abstract: The present invention relates to a peer to peer socket base system. The present invention particularly relates to the aforesaid peer-to-peer socket base system for multiuser audio and video VoIP call frame. The present invention addresses the bad server end and the same time high quality and reliable services for the users.Type: ApplicationFiled: November 12, 2021Publication date: May 18, 2023Inventors: SALAH M. WERFELLI, TANWIR ZAFAR SYEDMOHAMMAD
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Publication number: 20230154348Abstract: The present invention discloses a system for facilitating online learning. The present invention particularly relates to a system for facilitating online learning to teachers and students via video group call environment. The present invention comprises three portals i.e. admin portal, teachers portal and students portal.Type: ApplicationFiled: November 12, 2021Publication date: May 18, 2023Inventors: SALAH M. WERFELLI, SAM L. APPLETON, TANWIR ZAFAR SYEDMOHAMMAD
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Publication number: 20230026467Abstract: The present invention discloses systems and methods for multimedia processing. For example, the present invention provides systems and methods for receiving spoken audio, converting the spoken audio to text, and transferring the text to a user. As desired, the speech or text can be translated into one or more different languages. Systems and methods for real-time conversion and transmission of speech and text are provided, including systems and methods for large scale processing of multimedia events.Type: ApplicationFiled: July 21, 2021Publication date: January 26, 2023Inventors: SALAH M. WERFELLI, KHALED JASSIM J S AL-JABER, SULEIMAN KAYED SULEIMAN KHARROUB, KHALED MOHAMED ABDELBAKI ABDELHALIM REZK
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Publication number: 20230025800Abstract: The present invention relates to social media networking platform features. The present invention particularly relates to a system for the facilitation of speech synthesis i.e. text to speech or audio feature on a social media networking platform. The present invention further relates to the facilitation of speech recognition i.e. audio to text feature on social media networking platform. In addition, the aforementioned system also facilitates the feature of auto-translation in all languages to aid user operating in their own preferred language. Further, the aforementioned system enables sharing of content on its portal system while retaining the track and identity of the original creator of the content. The aforementioned system may be operated through all possible forms of multi-media platforms such as computers, laptops, mobiles, tablets etc.Type: ApplicationFiled: July 21, 2021Publication date: January 26, 2023Inventors: Salah M. Werfelli, Sam L. Appleton, Tanwir Zafar Syedmohammad
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Publication number: 20230025730Abstract: The present invention discloses a unique system for travel contemplation. The present invention particularly discloses a travel contemplating system with consolidating features of planning and navigating for site visits and accommodation at the same time simultaneously. In addition, the aforementioned system also provides integrated facilities of accessing all sorts of multimedia for entertainment while travelling.Type: ApplicationFiled: July 21, 2021Publication date: January 26, 2023Inventors: SALAH M. WERFELLI, SAM L. APPLETON, KHALED JASSIM J S AL-JABER, TANWIR ZAFAR SYEDMOHAMMAD
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Publication number: 20220231873Abstract: The present invention relates to a system for facilitating a comprehensive virtual or real-time meeting with accurate real-time translation. The present invention particularly relates to the afore-mentioned system wherein the aforesaid system may be utilised by direct room meetings or virtual meetings. The aforesaid system while facilitating communication with translation will have the capability of recording the whole event. In addition, the aforesaid system may further allows securing and saving the transcripts of whole meeting in text file and also secure the recorded conversation.Type: ApplicationFiled: January 19, 2022Publication date: July 21, 2022Inventors: SALAH M. WERFELLI, KHALED JASSIM J S AL-JABER, TANWIR ZAFAR SYEDMOHAMMAD
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Patent number: 9577640Abstract: Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. In other aspects, ESD circuitry is provided at corners of the IC layout and optionally within selected I/O slots. Decap circuitry is provided at an outer edge of the IC layout and is scalable in order to meet different requirements.Type: GrantFiled: June 2, 2014Date of Patent: February 21, 2017Assignee: Baysand Inc.Inventors: Jonathan C Park, Yin Hao Liew, Kok Seong Lee, Salah M Werfelli
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Patent number: 9401717Abstract: Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding.Type: GrantFiled: September 26, 2012Date of Patent: July 26, 2016Assignee: Baysand Inc.Inventors: Jonathan C Parks, Yin Hao Liew, Kok Seong Lee, Salah M Werfelli
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Patent number: 9166594Abstract: Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding.Type: GrantFiled: September 26, 2012Date of Patent: October 20, 2015Assignee: Baysand Inc.Inventors: Jonathan C Parks, Yin Hao Liew, Kok Seong Lee, Salah M Werfelli
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Patent number: 9166593Abstract: Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding.Type: GrantFiled: September 26, 2012Date of Patent: October 20, 2015Assignee: Baysand Inc.Inventors: Jonathan C Park, Yin Hao Liew, Kok Seong Lee, Salah M Werfelli
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Publication number: 20150048425Abstract: An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces of the upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit.Type: ApplicationFiled: July 21, 2014Publication date: February 19, 2015Inventors: Jonathan C. Park, Salah M. Werfelli, WeiZhi Kang, Wan Tat Hooi, Kok Siong Tee, Jeremy Jia Jian Lee
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Patent number: 8788984Abstract: An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces of the upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit.Type: GrantFiled: August 20, 2013Date of Patent: July 22, 2014Assignee: Baysand Inc.Inventors: Jonathan C Park, Salah M Werfelli, WeiZhi Kang, Wan Tat Hooi, Kok Siong Tee, Jeremy Jia Jian Lee
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Patent number: 8773163Abstract: Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding.Type: GrantFiled: September 26, 2012Date of Patent: July 8, 2014Assignee: Baysand Inc.Inventors: Jonathan C Park, Yin Hao Liew, Kok Seong Lee, Salah M Werfelli
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Publication number: 20130334576Abstract: An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces attic upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit.Type: ApplicationFiled: August 20, 2013Publication date: December 19, 2013Applicant: Baysand Inc.Inventors: Jonathan C Park, Salah M Werfelli, WeiZhi Kang, Wan Tat Hooi, Kok Siong Tee, Jeremy Jia Jian Lee
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Patent number: 8533641Abstract: Systems and methods are disclosed for forming a custom integrated circuit (IC) with a first fixed (non-programmable) region on a wafer with non-customizable mask layers, wherein the first fixed region includes multiplicities of transistors and a first interconnect layer and a second interconnect layer above the first interconnect layer which form base cells; and a programmable region above the first fixed region with customizable mask layers, wherein at least one mask layer in the programmable region is coupled to the second interconnect layer which provides electrical access to all transistor nodes of the base cells and wherein the programmable region comprises a third interconnect layer coupled to the customizable mask layers to customize the IC. A second fixed region may be formed above the programmable region to provide multiple fixed regions and reduce the number of required masks in customizing the custom IC.Type: GrantFiled: October 7, 2011Date of Patent: September 10, 2013Assignee: Baysand Inc.Inventors: Jonathan C Park, Salah M Werfelli, WeiZhi Kang, Wan Tat Hooi, Kok Siong Tee, Jeremy Jia Jian Lee
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Publication number: 20130087834Abstract: Systems and methods are disclosed for forming a custom integrated circuit (IC) with a first fixed (non-programmable) region on a wafer with non-customizable mask layers, wherein the first fixed region includes multiplicities of transistors and a first interconnect layer and a second interconnect layer above the first interconnect layer which form base cells; and a programmable region above the first fixed region with customizable mask layers, wherein at least one mask layer in the programmable region is coupled to the second interconnect layer which provides electrical access to all transistor nodes of the base cells and wherein the programmable region comprises a third interconnect layer coupled to the customizable mask layers to customize the IC. A second fixed region may be formed above the programmable region to provide multiple fixed regions and reduce the number of required masks in customizing the custom IC.Type: ApplicationFiled: October 7, 2011Publication date: April 11, 2013Inventors: Jonathan C. Park, Salah M. Werfelli, Weizhi Kang, Wan Tat Hooi, Kok Siong Tee, Jeremy Jia Jian Lee