Abstract: A communication device includes controller circuitry and transmitter circuitry. The controller circuitry determines a number of strings of consecutive ones in a data packet, and determines a number of stuffed bytes based on the number of strings of consecutive ones. Further, the controller circuitry schedules a transaction packet to be transmitted within a bus interval based on a determination that a total number of bytes of the transaction packet is less than a number of available bytes in the bus interval. The total number of bytes of the transaction packet is based on a number of payload bytes of the data packet and the number of stuffed bytes. The transmitter circuitry transmits the transaction packet during the bus interval based on the controller circuitry scheduling the transaction packet for transmission.

Abstract: A communication device includes controller circuitry and transmitter circuitry. The controller circuitry determines a number of strings of consecutive ones in a data packet, and determines a number of stuffed bytes based on the number of strings of consecutive ones. Further, the controller circuitry schedules a transaction packet to be transmitted within a bus interval based on a determination that a total number of bytes of the transaction packet is less than a number of available bytes in the bus interval. The total number of bytes of the transaction packet is based on a number of payload bytes of the data packet and the number of stuffed bytes. The transmitter circuitry transmits the transaction packet during the bus interval based on the controller circuitry scheduling the transaction packet for transmission.

Abstract: A method and system that selects an operational mode for a peripheral that has an interface engine block. When the peripheral operates in the operational mode a clock signal to the interface engine block is disabled for at least a portion of time.

Abstract: A method and system for selectively providing a gated clock signal to a control and status register block is provided. The method performs an operation by an application on a CSR block is provided. The operation may be programming a control register or reading a status register. The application detects when the operation is needed. If the operation is to be performed, a gated clock signal is enabled to the control and status register. The application then performs the operation on the control and status register block based on the gated clock signal. The gated clock signal may disabled after the operation has been performed. A system is provided for performing an operation on a control and status register block in a universal serial bus peripheral is provided. Clock gating logic detects when the operation is to be performed and provides a gated clock signal to the control and status register block when the operation is to be performed.

Abstract: A method and system in which a detection is made that an operation on a register and counter block is needed. A clock signal to the register and counter block is enabled, and the operation is executed on the register and counter block through employment of the clock signal.

Abstract: A method and system that selects an operational mode for a peripheral that has an interface engine block. When the peripheral operates in the operational mode a clock signal to the interface engine block is disabled for at least a portion of time.