Patents by Inventor Salem Eid

Salem Eid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Amplifiers and related receiver systems
    Patent number: 8704597
    Abstract: Apparatus are provided for amplifier circuits and related receiver systems. An amplifier circuit includes a first common-source amplification stage and a second common-source amplification stage. The input of the second common-source amplification stage is coupled to the output of the first common-source amplification stage such that the first common-source amplification stage generates a first amplified signal, and the second common-source amplification stage generates a second amplified signal based on the first amplified signal. The first common-source amplification stage is coupled to a first node and the second common-source amplification stage is coupled to a second node, wherein the common-source amplification stages are configured such that a current between the first node and the second node flows in series through the common-source amplification stages.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: April 22, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chuanzhao Yu, Salem Eid
  • AMPLIFIERS AND RELATED RECEIVER SYSTEMS
    Publication number: 20130241651
    Abstract: Apparatus are provided for amplifier circuits and related receiver systems. An amplifier circuit includes a first common-source amplification stage and a second common-source amplification stage. The input of the second common-source amplification stage is coupled to the output of the first common-source amplification stage such that the first common-source amplification stage generates a first amplified signal, and the second common-source amplification stage generates a second amplified signal based on the first amplified signal. The first common-source amplification stage is coupled to a first node and the second common-source amplification stage is coupled to a second node, wherein the common-source amplification stages are configured such that a current between the first node and the second node flows in series through the common-source amplification stages.
    Type: Application
    Filed: April 30, 2013
    Publication date: September 19, 2013
    Inventors: Chuanzhao YU, Salem EID
  • Amplifiers and related receiver systems
    Patent number: 8463226
    Abstract: Apparatus are provided for amplifier circuits and related receiver systems. An amplifier circuit includes a first common-source amplification stage and a second common-source amplification stage. The input of the second common-source amplification stage is coupled to the output of the first common-source amplification stage such that the first common-source amplification stage generates a first amplified signal, and the second common-source amplification stage generates a second amplified signal based on the first amplified signal. The first common-source amplification stage is coupled to a first node and the second common-source amplification stage is coupled to a second node, wherein the common-source amplification stages are configured such that a current between the first node and the second node flows in series through the common-source amplification stages.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: June 11, 2013
    Assignee: Freescale Semiconductors, Inc.
    Inventors: Chuanzhao Yu, Salem Eid
  • AMPLIFIERS AND RELATED RECEIVER SYSTEMS
    Publication number: 20120178400
    Abstract: Apparatus are provided for amplifier circuits and related receiver systems. An amplifier circuit includes a first common-source amplification stage and a second common-source amplification stage. The input of the second common-source amplification stage is coupled to the output of the first common-source amplification stage such that the first common-source amplification stage generates a first amplified signal, and the second common-source amplification stage generates a second amplified signal based on the first amplified signal. The first common-source amplification stage is coupled to a first node and the second common-source amplification stage is coupled to a second node, wherein the common-source amplification stages are configured such that a current between the first node and the second node flows in series through the common-source amplification stages.
    Type: Application
    Filed: January 11, 2011
    Publication date: July 12, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chuanzhao Yu, Salem Eid
  • Neutralization techniques for differential low noise amplifiers
    Patent number: 7256646
    Abstract: An differential LNA has first and second input MOS transistors, with differential inputs applied to their respective control gates and differential outputs taken at their respective drains. The gate-to-drain, Cgd, feedback capacitances of the first and second input MOS transistors are neutralized by respective gate-to-source, Cgs, capacitances in the two neutralizing MOS transistors. A first neutralizing MOS transistor has its control gate coupled to the control gate of the first input MOS transistor, its source node coupled to the drain node of the second input MOS transistor, and its drain node coupled to a fixed potential. A second neutralizing MOS transistor has its control gate coupled to the control gate of the second input MOS transistor, its source node coupled to the drain node of the first input MOS transistor, and its drain node coupled to the same fixed potential.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: August 14, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Salem Eid, Gregory A. Blum
  • Neutralization Techniques for differential low noise amplifiers
    Publication number: 20060284670
    Abstract: An differential LNA has first and second input MOS transistors, with differential inputs applied to their respective control gates and differential outputs taken at their respective drains. The gate-to-drain, Cgd, feedback capacitances of the first and second input MOS transistors are neutralized by respective gate-to-source, Cgs, capacitances in the two neutralizing MOS transistors. A first neutralizing MOS transistor has its control gate coupled to the control gate of the first input MOS transistor, its source node coupled to the drain node of the second input MOS transistor, and its drain node coupled to a fixed potential. A second neutralizing MOS transistor has its control gate coupled to the control gate of the second input MOS transistor, its source node coupled to the drain node of the first input MOS transistor, and its drain node coupled to the same fixed potential.
    Type: Application
    Filed: June 21, 2005
    Publication date: December 21, 2006
    Inventors: Salem Eid, Gregory Blum