Abstract: A device is configured to detect a zero voltage switching (ZVS) circuit output that includes a hard switching signal. The hard switching signal includes a false signal and a spike signal. Thereafter, the device generates digital pulse signals that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal, and uses the digital pulse signal that corresponds to the spike signal for adjusting a timing of a pulse width modulation (PWM) switching cycle.

Abstract: Methods, systems, and apparatus to facilitate a fault triggered diode emulation mode of a transistor. An example apparatus includes a driver to output a control signal to a gate terminal of a transistor of a power converter; and a diode emulation control circuit to, in response to determining a fault corresponding to the transistor, enable the transistor when current flows in a direction from a source terminal of the transistor to a drain terminal of the transistor.

Abstract: A control circuit for an inverter. The control circuit includes a first pulse width modulation (PWM) module configured to produce first and second complimentary PWM signals, and a second PWM module configured to produce a third and fourth complimentary PWM signals. PWM switching logic is coupled to the first and second PWM modules and is adapted to be coupled to a switch network. The switch network includes first, second, third, and fourth switches coupled in series between a first voltage terminal and a second voltage terminal. The PWM switching logic is configured to produce control signals for each of the first, second, third, and fourth switches in response to the first and second complimentary PWM signals and to the third and fourth complimentary PWM signals.

Abstract: Methods, systems, and apparatus to facilitate a fault triggered diode emulation mode of a transistor. An example apparatus includes a driver to output a control signal to a gate terminal of a transistor of a power converter; and a diode emulation control circuit to, in response to determining a fault corresponding to the transistor, enable the transistor when current flows in a direction from a source terminal of the transistor to a drain terminal of the transistor.

Abstract: Methods, systems, and apparatus to facilitate a fault triggered diode emulation mode of a transistor. An example apparatus includes a driver to output a control signal to a gate terminal of a transistor of a power converter; and a diode emulation control circuit to, in response to determining a fault corresponding to the transistor, enable the transistor when current flows in a direction from a source terminal of the transistor to a drain terminal of the transistor.

Abstract: A device is configured to detect a zero voltage switching (ZVS) circuit output that includes a hard switching signal. The hard switching signal includes a false signal and a spike signal. Thereafter, the device generates digital pulse signals that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal, and uses the digital pulse signal that corresponds to the spike signal for adjusting a timing of a pulse width modulation (PWM) switching cycle.

Abstract: A device [200] is configured to detect a zero voltage switching (ZVS) circuit [110] output that includes a hard switching signal. The hard switching signal [114] includes a false signal [116] and a spike signal [118]. Thereafter, the device generates digital pulse signals [312/314] that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal [312], and uses the digital pulse signal [314] that corresponds to the spike signal for adjusting a timing [132] of a pulse width modulation (PWM) switching cycle [Vgs ].

Abstract: Methods, systems, and apparatus to facilitate a fault triggered diode emulation mode of a transistor. An example apparatus includes a driver to output a control signal to a gate terminal of a transistor of a power converter; and a diode emulation control circuit to, in response to determining a fault corresponding to the transistor, enable the transistor when current flows in a direction from a source terminal of the transistor to a drain terminal of the transistor.

Abstract: In some examples, a gate driver includes a gate sense pin and a gate sense circuit configured to couple to a node of a transistor via the gate sense pin. The gate sense circuit includes an overcurrent detection circuit configured to detect a first fault condition based on the node before the transistor turns on in a soft switching mode. The gate sense circuit also includes a Miller plateau detection circuit configured to detect a second fault condition based on the node when the transistor is turning on in a hard switching mode.

Abstract: A device [200, para. 24] is configured to detect a zero voltage switching (ZVS) circuit [110, para. 14] output that includes a hard switching signal. The hard switching signal [114, para. 16] includes a false signal [116, para. 16] and a spike signal [118, para. 16]. Thereafter, the device generates digital pulse signals [312/314, para. 39] that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal [312, para. 41], and uses the digital pulse signal [314, para. 42] that corresponds to the spike signal for adjusting a timing [132, para. 20] of a pulse width modulation (PWM) switching cycle [Vgs 106, para. 32].

Abstract: In some examples, a gate driver includes a gate sense pin and a gate sense circuit configured to couple to a node of a transistor via the gate sense pin. The gate sense circuit includes an overcurrent detection circuit configured to detect a first fault condition based on the node before the transistor turns on in a soft switching mode. The gate sense circuit also includes a Miller plateau detection circuit configured to detect a second fault condition based on the node when the transistor is turning on in a hard switching mode.