Abstract: A method and implementing system is provided in which input signal specifications, element internal delays and output loads, for each element in a circuit design, are utilized in an iterative processing engine to objectively determine and provide a timing rule database for a circuit being designed. A schematic database netlist is run through a test model converter program to provide a test model database at a gate level for the test model design circuit. These data are processed by a designer through a workstation GUI and the result is applied to an I/O design testing function. The results of the I/O design testing function include a listing of patterns of input combinations which are needed to get listed outputs. The GUI prepares a sequence of stimuli to test the circuit with a timing simulator. Based on the output response of the timing simulator, delay relationships under various input and output load conditions are compiled.

Abstract: A cache sub-array arbitration circuit for receiving a plurality of address operands from a pending line of processor instructions in order to pre-fetch data needed in any memory access request in the pending instructions. The sub-array arbitration circuit compares at least two addresses corresponding to memory locations in the cache, and determines in which sub-arrays the memory locations reside. If the two memory locations reside in the same sub-array, the arbitration circuit sends the higher priority address to the sub-array. If a received address operand is the real address of a cache miss, the arbitration circuit sends the cache miss address to the sub-array before other pre-fetch memory access request.

Abstract: According to the present invention, a domino CMOS logic circuit having a plurality of stages for evaluating logic signals is provided. In one embodiment, the domino CMOS logic circuit includes at least one stage which has a logic block that includes a plurality of logic devices, inputs and outputs, and a precharge/evaluate circuit. In a more specific embodiment, the circuit includes a first transistor having a source connected to a supply voltage, a gate connected to a delayed clock signal, and a drain, a second transistor having a source connected to the drain of the first transistor, a gate connected to a clock signal, and a drain connected to the outputs of the logic block.

Abstract: A multiplier circuit within a CPU has its selections of partial products reordered in a unique manner so that shift left capabilities are eliminated and the hardware is required to only perform shift right operations. This allows for reduced circuit sizes in several components within the multiplier circuit in order to save area, speed computation time, and reduce power consumption on the chip.

Abstract: A "no select state" is implemented with self-resetting CMOS logic circuitry so as to essentially disable the resetting function of this logic circuitry when the logic circuitry is in an idle state. As an example, within a multiplier circuit in a processor, the selection inputs to a multiplexor circuit are de-selected when there is no need for the multiplier circuitry.