Abstract: A system is shown for interfacing between a work station or intelligent terminal device and a number of maintainable telecommunication systems. This system provides for interfacing between an intelligent CRT terminal and up to 26 remotely located maintenance processor units. This system provides the CRT attendant or crafts person with the ability to trouble-shoot or perform diagnostic testing upon a maintenance processor unit which is remotely located. In addition, the work station or intelligent terminal may be remotely located from the interface circuitry. This system establishes a connection between the work station or intelligent terminal and a particular maintenance processor unit. Once that connection is established, the maintenance processor unit of that telecommunications system reports diagnostic and trouble-shooting type information. This system also provides for manual reset and self test capabilities.

Abstract: A telecommunication system is provided consisting of a plurality of functional units each one producing a status signal. A maintenance processor is coupled to each of the functional units and receives the status signals. This processor produces signals representative of the status of the system. A remote alarm reporting unit is coupled to the processor and generates optically isolated alarm signals corresponding to the status representative signals generated by the processor.

Abstract: The bus extender circuit is a least replaceable unit which interfaces between intermodule subsystems and the microprocessor controller of the system. The bus extender circuits are structured so that the subsystem modules may be placed in different power zones. As a result, one subsystem may be powered down without affecting the other subsystems connected to the microprocessor's bus. In addition, the bus extender circuit converts from Fairchild Advanced Schottky TTL logic to high-speed CMOS logic and vice versa and allows bus interface gate arrays located in each subsystem to interface between the subsystem logic and the microprocessor. This bus extender circuit design eliminates the need for strapping options or DIP switches for address decoding.