Patents by Inventor Salim Rabaa
Salim Rabaa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11601119Abstract: A flip-flop circuit comprises a pass gate, a feedback inverter, and an interleaved filter. The pass gate comprises a clock input and an inverting clock input. The feedback inverter includes a feedback input coupled to both the clock input and the inverting clock input of the pass gate. The interleaved filter comprises a delay circuit including a delay output, a C-gate element, and a blocking inverter. The C-gate element includes a C-gate input and a C-gate output. The C-gate input is coupled to the delay output of the delay circuit and the pass gate, and the C-gate output is coupled to the feedback input of the feedback inverter. The blocking inverter includes a blocking input and a blocking output. The blocking input is coupled to the delay output of the delay circuit, and the blocking output is coupled to the feedback input of the feedback inverter.Type: GrantFiled: December 16, 2021Date of Patent: March 7, 2023Assignee: THE BOEING COMPANYInventors: Salim A. Rabaa, Ethan H. Cannon, Manuel F. Cabanas-Holmen
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Publication number: 20220200585Abstract: A flip-flop circuit comprises a pass gate, a feedback inverter, and an interleaved filter. The pass gate comprises a clock input and an inverting clock input. The feedback inverter includes a feedback input coupled to both the clock input and the inverting clock input of the pass gate. The interleaved filter comprises a delay circuit including a delay output, a C-gate element, and a blocking inverter. The C-gate element includes a C-gate input and a C-gate output. The C-gate input is coupled to the delay output of the delay circuit and the pass gate, and the C-gate output is coupled to the feedback input of the feedback inverter. The blocking inverter includes a blocking input and a blocking output. The blocking input is coupled to the delay output of the delay circuit, and the blocking output is coupled to the feedback input of the feedback inverter.Type: ApplicationFiled: December 16, 2021Publication date: June 23, 2022Inventors: Salim A. Rabaa, Ethan H. Cannon, Manuel F. Cabanas-Holmen
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Patent number: 10734998Abstract: Systems, methods, and apparatus for complementary self-limiting logic are disclosed. In one or more embodiments, a method for mitigating errors caused by transients in a logic gate transistor comprises biasing, by a first stage of transistors, a second stage of transistors such that a voltage potential across terminals of each of the transistors of the second stage are at an equal voltage potential. The method further comprises biasing, by the second stage of transistors, the logic gate transistor such that a voltage potential across terminals of the logic gate transistor are at an equal voltage potential, thereby ensuring that the transients will not cause the logic gate transistor to erroneously change logic states when the logic gate transistor is in a logically off state.Type: GrantFiled: May 31, 2019Date of Patent: August 4, 2020Assignee: The Boeing CompanyInventors: Manuel Cabanas-Holmen, Jeff Maharrey, Salim Rabaa
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Patent number: 9013219Abstract: A flip flop circuit has a first stage and a second stage. The first stage and the second stage each have interleaved filters.Type: GrantFiled: September 11, 2013Date of Patent: April 21, 2015Assignee: The Boeing CompanyInventors: Manuel F. Cabanas-Holmen, Ethan Cannon, Salim A. Rabaa
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Publication number: 20150070062Abstract: A flip flop circuit has a first stage and a second stage. The first stage and the second stage each have interleaved filters.Type: ApplicationFiled: September 11, 2013Publication date: March 12, 2015Applicant: The Boeing CompanyInventors: Manuel F. Cabanas-Holmen, Ethan Cannon, Salim A. Rabaa
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Patent number: 8847621Abstract: A circuit and methods for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits are presented. A primary logic output is generated from a primary logic gate in response to an input. A redundant logic output is generated from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present. An interleaved C-gate output is generated from an interleaved C-gate that emulates an inverter output when the primary logic output and the redundant logic output match, and does not changes its output when the primary logic output and the redundant logic output do not match during the SEE.Type: GrantFiled: July 16, 2012Date of Patent: September 30, 2014Assignee: The Boeing CompanyInventors: Ethan Cannon, Salim Rabaa, Josh Mackler
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Patent number: 8754701Abstract: An interleaved filter circuit has a delay element configured to receive an input signal. An interleaved output buffer has a first input which receives the input signal and a second input which receives the output of the delay element. An output of the interleaved output buffer is driven when the first input and the second input are at a same logic level.Type: GrantFiled: November 9, 2012Date of Patent: June 17, 2014Assignee: The Boeing CompanyInventors: Ethan Cannon, Manuel F. Cabanas-Holmen, Salim A. Rabaa
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Publication number: 20140015564Abstract: A circuit and methods for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits are presented. A primary logic output is generated from a primary logic gate in response to an input. A redundant logic output is generated from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present. An interleaved C-gate output is generated from an interleaved C-gate that emulates an inverter output when the primary logic output and the redundant logic output match, and does not changes its output when the primary logic output and the redundant logic output do not match during the SEE.Type: ApplicationFiled: July 16, 2012Publication date: January 16, 2014Inventors: Ethan Cannon, Salim Rabaa, Josh Mackler
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Patent number: 8207753Abstract: The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.Type: GrantFiled: January 27, 2011Date of Patent: June 26, 2012Assignee: The Boeing CompanyInventors: Manuel F. Cabanas-Holmen, Ethan H. Cannon, Salim A. Rabaa
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Publication number: 20110309856Abstract: The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.Type: ApplicationFiled: January 27, 2011Publication date: December 22, 2011Applicant: THE BOEING COMPANYInventors: Manuel F. Cabanas-Holmen, Ethan H. Cannon, Salim A. Rabaa
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Patent number: 8054099Abstract: The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.Type: GrantFiled: July 29, 2009Date of Patent: November 8, 2011Assignee: The Boeing CompanyInventors: Manuel F. Cabanas-Holmen, Ethan H. Cannon, Salim A. Rabaa
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Publication number: 20110025372Abstract: The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.Type: ApplicationFiled: July 29, 2009Publication date: February 3, 2011Applicant: THE BOEING COMPANYInventors: Manuel F. Cabanas-Holmen, Ethan H. Cannon, Salim A. Rabaa