Patents by Inventor Saliya Witharana

Saliya Witharana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming copper layers
    Patent number: 7413936
    Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: August 19, 2008
    Assignee: Intel Corporation
    Inventors: Hamid Azimi, Debabrata Gupta, Saliya Witharana
  • Low cost programmable CPU package/substrate
    Publication number: 20060060946
    Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.
    Type: Application
    Filed: November 9, 2005
    Publication date: March 23, 2006
    Inventors: Hamid Azimi, Debabrata Gupta, Saliya Witharana
  • Low cost programmable CPU package/substrate
    Patent number: 7005727
    Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: February 28, 2006
    Assignee: Intel Corporation
    Inventors: Hamid Azimi, Debabrata Gupta, Saliya Witharana
  • Low cost programmable CPU package/substrate
    Publication number: 20040004232
    Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.
    Type: Application
    Filed: September 3, 2002
    Publication date: January 8, 2004
    Inventors: Hamid Azimi, Debabrata Gupta, Saliya Witharana