Patents by Inventor SALMAN LATIF
SALMAN LATIF has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11893185Abstract: Systems, methods, and devices are described that may mitigate pixel and touch crosstalk noise. A touch processing system may compensate touch scan data to reduce the noise based on a luminance value. An image processing system may determine the luminance value based on image data and a display brightness value of an electronic display. Using the compensated touch scan data, the touch processing system may determine a proximity of a capacitive object to at least one touch sense region of the electronic display.Type: GrantFiled: September 6, 2022Date of Patent: February 6, 2024Assignee: Apple Inc.Inventors: Salman Latif, Si Mohamed Aziz Sbai, Mahesh B Chappalli, Marc J DeVincentis, Timothy M Henigan, Sanjay Mani, Rohit Natarajan, Paolo Sacchetto, Rohit K Gupta, Meir Harar
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Publication number: 20230223406Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.Type: ApplicationFiled: March 17, 2023Publication date: July 13, 2023Applicant: Tahoe Research, Ltd.Inventors: Tahir GHANI, Salman Latif, Chanaka D. Munasinghe
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Patent number: 11631673Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.Type: GrantFiled: February 23, 2021Date of Patent: April 18, 2023Assignee: Tahoe Research, Ltd.Inventors: Tahir Ghani, Salman Latif, Chanaka D. Munasinghe
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Publication number: 20230093204Abstract: Systems, methods, and devices are described that may mitigate pixel and touch crosstalk noise. A touch processing system may compensate touch scan data to reduce the noise based on a luminance value. An image processing system may determine the luminance value based on image data and a display brightness value of an electronic display. Using the compensated touch scan data, the touch processing system may determine a proximity of a capacitive object to at least one touch sense region of the electronic display.Type: ApplicationFiled: September 6, 2022Publication date: March 23, 2023Inventors: Salman Latif, Si Mohamed Aziz Sbai, Mahesh B Chappalli, Marc J DeVincentis, Timothy M Henigan, Sanjay Mani, Rohit Natarajan, Paolo Sacchetto, Rohit K Gupta, Meir Harar
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Publication number: 20210175233Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.Type: ApplicationFiled: February 23, 2021Publication date: June 10, 2021Inventors: Tahir GHANI, Salman LATIF, Chanaka D. MUNASINGHE
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Patent number: 10964697Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.Type: GrantFiled: March 9, 2020Date of Patent: March 30, 2021Assignee: Intel CorporationInventors: Tahir Ghani, Salman Latif, Chanaka D. Munasinghe
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Publication number: 20200212039Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.Type: ApplicationFiled: March 9, 2020Publication date: July 2, 2020Inventors: Tahir GHANI, Salman LATIF, Chanaka D. MUNASINGHE
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Patent number: 10622359Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.Type: GrantFiled: July 12, 2019Date of Patent: April 14, 2020Assignee: Intel CorporationInventors: Tahir Ghani, Salman Latif, Chanaka D. Munasinghe
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Publication number: 20190341383Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.Type: ApplicationFiled: July 12, 2019Publication date: November 7, 2019Inventors: Tahir GHANI, Salman LATIF, Chanaka D. MUNASINGHE
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Patent number: 10396079Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.Type: GrantFiled: August 14, 2018Date of Patent: August 27, 2019Assignee: Intel CorporationInventors: Tahir Ghani, Salman Latif, Chanaka D. Munasinghe
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Publication number: 20190006362Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.Type: ApplicationFiled: August 14, 2018Publication date: January 3, 2019Inventors: Tahir GHANI, Salman LATIF, Chanaka D. MUNASINGHE
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Patent number: 10069658Abstract: Embodiments include a pulsed decision feedback equalization (DFE) circuit. The DFE circuit may include a current integrating summer (CIS) circuit that passes one or more data signals on respective data nodes based on an input data signal and a clock signal. The DFE circuit may further include a correction circuit, such as a current digital-to-analog converter (IDAC) circuit, that may provide a correction circuit to a data node based on a prior bit of the input data signal. The correction circuit may provide a conductive path between a current source of the correction circuit and the data node for a time period that is less than the unit interval (UI) of the clock signal and/or data signal. The DFE circuit may include a plurality of correction circuits to provide respective correction signals based on different prior bits of the input data signal. Other embodiments may be described and claimed.Type: GrantFiled: September 23, 2015Date of Patent: September 4, 2018Assignee: INTEL CORPORATIONInventors: Salman Latif, Ravindran Mohanavelu, Sitaraman V. Iyer
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Patent number: 10056380Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.Type: GrantFiled: June 20, 2013Date of Patent: August 21, 2018Assignee: Intel CorporationInventors: Tahir Ghani, Salman Latif, Chanaka D. Munasinghe
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Publication number: 20170085399Abstract: Embodiments include a pulsed decision feedback equalization (DFE) circuit. The DFE circuit may include a current integrating summer (CIS) circuit that passes one or more data signals on respective data nodes based on an input data signal and a clock signal. The DFE circuit may further include a correction circuit, such as a current digital-to-analog converter (IDAC) circuit, that may provide a correction circuit to a data node based on a prior bit of the input data signal. The correction circuit may provide a conductive path between a current source of the correction circuit and the data node for a time period that is less than the unit interval (UI) of the clock signal and/or data signal. The DFE circuit may include a plurality of correction circuits to provide respective correction signals based on different prior bits of the input data signal. Other embodiments may be described and claimed.Type: ApplicationFiled: September 23, 2015Publication date: March 23, 2017Inventors: Salman Latif, Ravindran Mohanavelu, Sitaraman V. Iyer
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Publication number: 20160056156Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.Type: ApplicationFiled: June 20, 2013Publication date: February 25, 2016Inventors: TAHIR GHANI, SALMAN LATIF, CHANAKA D. MUNASINGHE