Abstract: Apparatuses and methods are presented relating to a plurality of current sources for generating a plurality of first bias currents to drive a plurality of LEDs and a plurality of measurement circuits for obtaining a plurality of first voltage measurements for the LEDs during a first test cycle. The current sources are further configurable to generate a plurality of second bias currents for driving the LEDs, and the measurement circuits are further configurable to obtain a plurality of second voltage measurements for the plurality of LEDs, during a second test cycle. A memory device is configured to store the first and second bias currents and first and second voltage measurements as a current-voltage (I-V) performance characteristic.

Abstract: Apparatuses and methods are presented relating to a plurality of current sources for generating a plurality of first bias currents to drive a plurality of LEDs and a plurality of measurement circuits for obtaining a plurality of first voltage measurements for the LEDs during a first test cycle. The current sources are further configurable to generate a plurality of second bias currents for driving the LEDs, and the measurement circuits are further configurable to obtain a plurality of second voltage measurements for the plurality of LEDs, during a second test cycle. A memory device is configured to store the first and second bias currents and first and second voltage measurements as a current-voltage (I-V) performance characteristic.

Abstract: Systems and methods for wireless power transfer with fractional timing resolution are described. In some embodiments, an electrical power transmitter may include a transistor and a rising edge control circuit configured to control a gate of the transistor to produce a rising edge of a pulse at a time selected with a resolution greater than a full-clock period.

Abstract: Systems and methods for wireless power transfer with fractional timing resolution are described. In some embodiments, an electrical power transmitter may include a transistor and a rising edge control circuit configured to control a gate of the transistor to produce a rising edge of a pulse at a time selected with a resolution greater than a full-clock period.

Abstract: The invention provides a receiver for use in a wireless communication system that substantially reduces mismatch between an in-phase (I) component and a quadrature (Q) component of a received signal. The receiver achieves this by sharing or “ping-ponging” an analog-to-digital converter (ADC) between the I and Q components. By sharing a single pipelined ADC between the I and Q components, both the I and Q components are processed by the same circuitry inside the pipelined ADC thereby eliminating many dominant sources of I-Q mismatch. The pipelined ADC operates at approximately twice the speed as other circuit components. Consequently, I-Q mismatch, which negatively affects performance, may be substantially reduced. At the same time, system complexity, cost, and power dissipation are reduced by eliminating an additional ADC typically used to process the I and Q components in parallel signal paths.

Abstract: The invention provides a receiver for use in a wireless communication system that substantially reduces mismatch between an in-phase (I) component and a quadrature (Q) component of a received signal. The receiver achieves this by sharing or “ping-ponging” an analog-to-digital converter (ADC) between the I and Q components. By sharing a single pipelined ADC between the I and Q components, both the I and Q components are processed by the same circuitry inside the pipelined ADC thereby eliminating many dominant sources of I-Q mismatch. The pipelined ADC operates at approximately twice the speed as other circuit components. Consequently, I-Q mismatch, which negatively affects performance, may be substantially reduced. At the same time, system complexity, cost, and power dissipation are reduced by eliminating an additional ADC typically used to process the I and Q components in parallel signal paths.

Abstract: An integrated, tuning circuit for tuning a MOSFET-C filter contains a tuning MOSFET and a differential amplifier. A current source is connected to the drain of the tuning MOSFET. The output of the amplifier is coupled to the drain of the tuning MOSFET and to a terminal that connects to the drains of the MOSFETs of the filter, so that the equivalent resistance of the filter is dependant on the current. The current source is coupled to a reference current generator, such that current supplied by the current source to the tuning MOSFET is proportional to the current supplied in the reference current generator, which in turn varies with process and environmental conditions of a capacitance. As a result, changes in process and environmental conditions oppositely affect the capacitance and resistance in the filter, resulting in a fixed RC product and fixed frequency response from the filter.

Abstract: An apparatus for demodulating two pilot tones for use by a servo control for a magnetic read head is disclosed. The apparatus provides positioning information to position the read head adjacent to a desired information track of a magnetic storage medium. The apparatus comprises a first and a second pilot tone demodulation unit. Each pilot tone demodulation unit comprises a band pass filter for providing a first filtered output signal having an amplitude and a phase representative of the first and the second frequency pilot tones, respectively. A delay lock loop receives the first filtered out of the band pass filter and determines a phase of the frequency pilot tone. A multiplier is connected to the output of the band pass filter and the output of the delay lock loop for multiplying the frequency pilot tone with the output signal of the delay lock loop. A low pass filter is connected to the output of the multiplier for filtering out undesired signals and for passing a DC signal.