Patents by Inventor Saloni Goel

Saloni Goel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240070040
    Abstract: Apparatuses, systems, and techniques to help processing resources used cause one or more systems in a distributed computing environment to be checked by one or more checks. In at least one embodiment, said one or more checks help identify one or more unhealthy nodes based, at least in part, on how many nodes are in a workload.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 29, 2024
    Inventors: Nivedita Viswanath, Li Ge, Sanjay Chatterjee, Saloni Goel, Namit Dhameja, Abhijit Prakash Paithankar, Dileep Ranganathan, Raghav Hrishikeshan Mukundan
  • Publication number: 20240069978
    Abstract: Apparatuses, systems, and techniques to select computer systems to perform portions of one or more programs in parallel based, at least in part, on the computer systems' ability to perform the portions at substantially a same performance level. In at least one embodiment, a system includes one or more circuits to select one or more computer systems based, at least in part, on identifying one or more logical partitions of the computer systems based, at least in part, on one or more attributes of one or more programs associated with the one or more computer systems.
    Type: Application
    Filed: February 10, 2023
    Publication date: February 29, 2024
    Inventors: Arpit Singh, Sanjay Chatterjee, Santosh Bahir, Nivedita Viswanath, Sukesh Roy, Saloni Goel, Neeraj Kapoor
  • Publication number: 20240069964
    Abstract: Apparatuses, systems, and techniques for scheduling instructions in a cluster to guarantee GPU-CPU alignment for these instructions. In at least one embodiment, jobs are scheduled based on constraints on job sizes and job placement. In at least one embodiment, a processor comprises circuits to schedule instructions to be performed by processors based on latency of interconnects coupled to these processors.
    Type: Application
    Filed: July 21, 2023
    Publication date: February 29, 2024
    Applicant: NVIDIA Corporation
    Inventors: Sanjay Chatterjee, Nivedita Viswanath, Kevin Alan Klues, Saloni Goel, Arpit Singh
  • Publication number: 20240070047
    Abstract: Apparatuses, systems, and techniques to schedule one or more workloads to one or more computers by comparing one or more performance metrics of the one or more workloads to be performed using one or more computers with one or more performance metrics of the one or more workloads to be performed using a simulation of the one or more computers.
    Type: Application
    Filed: February 10, 2023
    Publication date: February 29, 2024
    Inventors: Sanjay Chatterjee, Saloni Goel, Nivedita Viswanath, Sukesh Roy