Abstract: A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.

Abstract: A processor comprising a decoder, an execution core and a bus controller. The decoder is operative to decode instructions received by the processor including a move instruction comprising a first operand identifying a plurality of bytes of packed data and a second operand identifying a corresponding plurality of byte masks. The execution core, coupled to the decoder, is operative to receive the decoded move instruction and analyze each individual byte mask of the plurality of byte masks to identify corresponding bytes within the plurality of bytes of packed data that are write-enabled. The bus controller, coupled to the execution core, is operative to write select bytes of the plurality of bytes of packed data to an implicitly defined location based, at least in part, on the write enabled byte masks identified by the execution core.

Abstract: An apparatus and method of optimizing write combining operations using write combining buffers. A plurality of control fields are assigned to each of the write combining buffers. Each of the control fields has a value corresponding to one of a plurality of write combining states. A first of the plurality of write combining states transitions to a second of the plurality of write combining states in response to a write combining operation.

Abstract: The present invention discloses a method and apparatus for synchronizing weakly ordered write combining operations. A memory controller has a buffer to service memory accesses. A store fence instruction is dispatched to the memory controller. If the buffer contains at least a data written by at least one of the weakly ordered write combining operations prior to the store fence instruction, then the store fence instruction is blocked until a block in the buffer containing the data is globally observed. If the buffer does not contain any data written by at least one of the write combining operations prior to the store fence instruction, then the store fence instruction is accepted by the memory controller.