Patents by Inventor Salvador Salcido

Salvador Salcido has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7313372
    Abstract: A second single-ended receiver having a first stage for receiving an input signal and outputting a pair of corresponding output signals, and a second stage for receiving the pair of output signals and outputting a corresponding single output signal. First and second pull-down transistors are coupled to first and second inputs to the first stage. A bias circuit electrically biases the first stage, second stage, and first and second pull-down transistors, and a power supply provides power to those components.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: December 25, 2007
    Assignee: Avago Technologies General IP Pte Ltd
    Inventors: Manuel Salcido, Gilbert Yoh, Guy Humphrey, Salvador Salcido
  • Patent number: 7202546
    Abstract: An integrated circuit including a copper interconnection layer includes an aluminum distribution layer overlying the copper interconnection layer to distribute external electrical signals such as power, ground, and clock signals throughout the die of the device. The distribution layer overlies the copper interconnection layer in a grid pattern which connects to the copper interconnection layer through a plurality of vias. The distribution layer further includes a plurality of wire bond pads to permit wire bonding between the distribution layer and bonding pads of the integrated circuit package.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: April 10, 2007
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Salvador Salcido, Jr., Michael G. Kelly, Michael D. Cusack, Ravindhar K. Kaw
  • Publication number: 20060025089
    Abstract: A second single-ended receiver having a first stage for receiving an input signal and outputting a pair of corresponding output signals, and a second stage for receiving the pair of output signals and outputting a corresponding single output signal. First and second pull-down transistors are coupled to first and second inputs to the first stage. A bias circuit electrically biases the first stage, second stage, and first and second pull-down transistors, and a power supply provides power to those components.
    Type: Application
    Filed: July 29, 2004
    Publication date: February 2, 2006
    Inventors: Manuel Salcido, Gilbert Yoh, Guy Humphrey, Salvador Salcido
  • Publication number: 20050082675
    Abstract: An integrated circuit including a copper interconnection layer includes an aluminum distribution layer overlying the copper interconnection layer to distribute external electrical signals such as power, ground, and clock signals throughout the die of the device. The distribution layer overlies the copper interconnection layer in a grid pattern which connects to the copper interconnection layer through a plurality of vias. The distribution layer further includes a plurality of wire bond pads to permit wire bonding between the distribution layer and bonding pads of the integrated circuit package.
    Type: Application
    Filed: October 3, 2003
    Publication date: April 21, 2005
    Inventors: Salvador Salcido, Michael Kelly, Michael Cusack, Ravindhar Kaw
  • Patent number: 6766155
    Abstract: A novel terminating differential bus receiver with automatic compensation for process, voltage, and temperature variation is presented. A termination circuit is connected internal to the integrated circuit to the input of a differential receiver in parallel with a transmission line connectable to the receiver. Both the termination circuit and the differential receiver are implemented with at least one p-channel transistor and at least one n-channel transistor, such that the p-channel transistors of the termination circuit and receiver and the n-channel transistors of the termination circuit and receiver are ratioed to vary similarly under PVT variation.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: July 20, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Manuel Salcido, Salvador Salcido, Jr., Scott T. Evans, Gilbert Yoh
  • Patent number: 6714039
    Abstract: An active termination technique for reducing the propagation delay of a signal across a transmission line is presented. In accordance with a preferred embodiment of the invention, repeaters along a transmission line are paired with active termination circuits in very close proximity to the repeater in order to prevent signal reflections caused by the repeaters. The repeaters and associated active termination circuits are implemented with at least one PFET and at least one NFET, each having the same transistor gate lengths. The PFETs and the NFETs in the repeater and associated termination are ratioed to vary similarly over process/voltage/temperature variation.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: March 30, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Manuel Salcido, Gilbert Yoh, Salvador Salcido, Jr., Scott T. Evans
  • Publication number: 20030210070
    Abstract: An active termination technique for reducing the propagation delay of a signal across a transmission line is presented. In accordance with a preferred embodiment of the invention, repeaters along a transmission line are paired with active termination circuits in very close proximity to the repeater in order to prevent signal reflections caused by the repeaters. The repeaters and associated active termination circuits are implemented with at least one PFET and at least one NFET, each having the same transistor gate lengths. The PFETs and the NFETs in the repeater and associated termination are ratioed to vary similarly over process/voltage/temperature variation.
    Type: Application
    Filed: May 13, 2002
    Publication date: November 13, 2003
    Inventors: Manuel Salcido, Gilbert Yoh, Salvador Salcido, Scott T. Evans
  • Publication number: 20030139164
    Abstract: A novel terminating differential bus receiver with automatic compensation for process, voltage, and temperature variation is presented. A termination circuit is connected internal to the integrated circuit to the input of a differential receiver in parallel with a transmission line connectable to the receiver. Both the termination circuit and the differential receiver are implemented with at least one p-channel transistor and at least one n-channel transistor, such that the p-channel transistors of the termination circuit and receiver and the n-channel transistors of the termination circuit and receiver are ratioed to vary similarly under PVT variation.
    Type: Application
    Filed: January 24, 2002
    Publication date: July 24, 2003
    Inventors: Manuel Salcido, Salvador Salcido, Scott T. Evans, Gilbert Yoh
  • Patent number: 6533387
    Abstract: An inkjet printing system includes a print media transport assembly which routes a print medium through the inkjet printing system, a carriage assembly which holds an inkjet printhead assembly and traverse the print medium, and a single motor operatively coupled to both the print media transport assembly and the carriage assembly. As such, the single motor selectively drives both the print media transport assembly and the carriage assembly.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: March 18, 2003
    Assignee: Agilent Technologies, Inc.
    Inventors: Laura Elisabeth Simmons, Salvador Salcido, Jr.
  • Patent number: 6476486
    Abstract: A low inductance integrated circuit package such as a ball grid array package in which is provided a electronic device that enhances performance on an integrated circuit mounted in the die attachment region of the package. The electronic device may be either passive or active and may include such devices as sensors, Zener diodes, voltage regulators, chip based devices, etc. Provision of such devices in a ball grid array package creates a cost effective way of improving the performance on an integrated circuit mounted in that package.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: November 5, 2002
    Assignee: Agilent Technologies, Inc.
    Inventors: Tamio Humphrey, Salvador Salcido, Jr.
  • Publication number: 20020149642
    Abstract: An inkjet printing system includes a print media transport assembly which routes a print medium through the inkjet printing system, a carriage assembly which holds an inkjet printhead assembly and traverse the print medium, and a single motor operatively coupled to both the print media transport assembly and the carriage assembly. As such, the single motor selectively drives both the print media transport assembly and the carriage assembly.
    Type: Application
    Filed: April 11, 2001
    Publication date: October 17, 2002
    Inventors: Laura Elisabeth Simmons, Salvador Salcido