Abstract: A method and apparatus for performing direct memory address (DMA) operations between a requestor and responder device by prestoring, for each device, a logical token and offset value which is recognizable by the device as an indicia to identify one or more local memory addresses within the device, and initiating a DMA operation within the requestor device by the requestor device transferring the token and offset value to the responder device, the responder device identifying a responder device local memory address by translation of the token and offset value, and the responder device accessing the identified responder local memory address for data transfer, associated with the token and offset, and the requestor device identifying a requestor device local memory address for completing the data transfer.

Abstract: A channel subsystem with a conventional serial extender link that causes communications between a channel and a control unit to be delayed by the additional time to transmit a message in one direction and to transmit an acknowledgement in the other direction. The channel subsystem also has a buffer and associated components (called a channel outboard box) that are used for prefetching data from processor memory or from a peripheral device without waiting for the acknowledgment routines that are commonly used on both an interlocked data transfer and a non-interlocked transfer (called data streaming). A system of counters and other components and associated operations maintain the correct byte count that would otherwise be maintained in a system without the prefetch buffer and with only a short serial link. A system of count and status frames provides for sending byte count and other status information between the channel and the outboard box.