Abstract: A field effect device transistor geometry and method of fabrication are described. The FET may be operated from a bias potential that forms an electrical field within the device exceeding a predetermined field strength. The device comprises a semiconductor substrate portion of a first conductivity type, said substrate portion having a major surface, and a region of a second conductivity type adjacent the major surface and adapted to receive the predetermined bias potential, the region including a subregion of like conductivity type and lesser conductivity, the subregion being positioned within the region such that the subregion receives at least that portion of the dipole electrical field including and exceeding the predetermined value.

Abstract: An integrated circuit device for protecting the circuitry of an integrated circuit from an electrostatic discharge into an output pin of the chip is disclosed. In a preferred embodiment, the device comprises an n-well, n-channel, polysilicon-gated FET structure, which operates in a punch-through mode, coupled to an output pad and an output buffer of the circuit. Back biasing in the chip system affords additional inhibition to turn-on during normal system operation.