Patents by Inventor Salvatore Coffa

Salvatore Coffa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6943390
    Abstract: The high-gain photodetector is formed in a semiconductor-material body which houses a PN junction and a sensitive region that is doped with rare earths, for example erbium. The PN junction forms an acceleration and gain region separate from the sensitive region. The PN junction is reverse-biased and generates an extensive depletion region accommodating the sensitive region. Thereby, the incident photon having a frequency equal to the absorption frequency of the used rare earth crosses the PN junction, which is transparent to light, can be captured by an erbium ion in the sensitive region, so as to generate a primary electron, which is accelerated towards the PN junction by the electric field present, and can, in turn, generate secondary electrons by impact, according to an avalanche process. Thereby, a single photon can give rise to a cascade of electrons, thus considerably increasing detection efficiency.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: September 13, 2005
    Assignee: STMicroelectronics S.r.l.
    Inventors: Salvatore Coffa, Sebania Libertino, Ferruccio Frisina
  • Publication number: 20050031927
    Abstract: A polyelectrolyte membrane includes at least one syndiotactic styrenic polymer or copolymer in its clathrate form. The syndiotactic styrenic polymer or copolymer in its clathrate form is syndiotactic polystyrene. The polyelectrolyte membrane has a good electrical conductivity as well as good mechanical properties. This type of membrane is used for fuel cells and similar electrochemical applications.
    Type: Application
    Filed: June 29, 2004
    Publication date: February 10, 2005
    Applicant: STMicroelectronics S.r.l.
    Inventors: Teresa Napolitano, Salvatore Coffa, Giuseppe Mensitieri, Anna Borriello, Luigi Nicolais
  • Publication number: 20050017251
    Abstract: The present invention relates to a new light emitters that exploit the use of semiconducting single walled carbon nanotubes (SWNTs). Experimental evidences are given on how it is possible, within the standard silicon technology, to devise light emitting diodes (LEDs) emitting in the infrared IR where light emission results from a radiative recombination of electron and holes on semiconducting single walled carbon nanotubes (SWNTs-LED). We will also show how it is possible to implement these SWNTs-LED in order to build up a laser source based on the emission properties of SWNTs. A description of the manufacturing process of such devices is also given.
    Type: Application
    Filed: June 14, 2004
    Publication date: January 27, 2005
    Applicant: STMicroelectronics S.r.l.
    Inventors: Vincenzo Vinciguerra, Francesco Buonocore, Maria Bevilacqua, Salvatore Coffa
  • Publication number: 20040248349
    Abstract: A method for manufacturing a semiconductor substrate of a first concentration type is described, which comprises at least a buried insulating cavity, comprising the following steps:
    Type: Application
    Filed: December 1, 2003
    Publication date: December 9, 2004
    Applicant: STMicroelectronics S.r.l.
    Inventors: Crocifisso Marco Antonio Renna, Luigi La Magna, Simona Lorenti, Salvatore Coffa
  • Patent number: 6828598
    Abstract: A semiconductor device for electro-optic applications includes a rare-earth ions doped P/N junction integrated on a semiconductor substrate. The semiconductor device may be used to obtain laser action in silicon. The rare-earth ions are in a depletion layer of the doped P/N junction, and are for providing a coherent light source cooperating with a waveguide defined by the doped P/N junction. The doped P/N junction may be the base-collector region of a bipolar transistor, and is reverse biased so that the rare-earth ions provide the coherent light.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: December 7, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Salvatore Coffa, Sebania Libertino, Mario Saggio, Ferruccio Frisina
  • Patent number: 6774061
    Abstract: A process for forming a thin layer of Silicon nanocrystals in an oxide layer is disclosed. The process includes, on a semiconductive substrate, thermally oxidizing a first portion of the substrate into an oxide layer, forming Silicon ions within the layer of oxide, and thermally treating the Silicon ions to become the thin layer of Silicon nanocrystals. In the inventive process the formation of the Silicon ions is by ionic implantation of the Silicon ions into the oxide at an ionization energy of between 0.1 keV and 7 keV, and preferably between 1 and 5 keV. This allows the Silicon atoms to coalesce in a lower temperature than would otherwise be possible. Additionally, more than one layer of nanocrystals can be formed by performing more than one implantation at more than one energy level. Embodiments of the invention can be used to form non-volatile memory devices with a very high quality having a very small size.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: August 10, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Salvatore Coffa, Davide Patti
  • Patent number: 6743654
    Abstract: A method of making a monolithically integrated pressure sensor includes making a cavity in the semiconductor substrate. This may be formed by plasma etching the front side or the back side of the silicon wafer to cut a plurality of trenches or holes deep enough to extend for at least part of its thickness into a doped buried layer of opposite type of conductivity of the substrate and of the epitaxial layer grown over it. The method may also include electrochemically etching through such trenches, and the silicon of the buried layer with an electrolytic solution suitable for selectively etching the doped silicon of the opposite type of conductivity, thereby making the silicon of the buried layer porous. The method may also include oxidizing and leaching away the silicon so made porous.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: June 1, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Salvatore Coffa, Luigi Occhipinti
  • Patent number: 6506658
    Abstract: A method for fabricating a silicon-on-insulator (SOI) wafer that includes a monocrystalline silicon substrate with a doped region buried therein is provided. The method includes forming a plurality of trench-like openings extending from a surface of the substrate to the doped buried region, and selectively etching through the plurality of trench-like openings to change the doped buried region into a porous silicon region. The porous silicon region is oxidized to obtain an insulating region for the SOI wafer.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: January 14, 2003
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe D'Arrigo, Corrado Spinella, Salvatore Coffa, Giuseppe Arena, Marco Camalleri
  • Publication number: 20030003347
    Abstract: A fuel cell for an electrical load circuit includes a first monocrystalline silicon substrate and a positive half-cell formed therein, and a second monocrystalline silicon substrate and a positive half-cell formed therein. Each half-cell includes a microporous catalytic electrode permeable to a gas and connectable to the electrical load circuit. A cell area is defined on a surface of each respective monocrystalline silicon substrate, and includes a plurality of parallel trenches formed therein for receiving the gas to be fed to the respective microporous catalytic electrode. A cation exchange membrane separates the two microporous catalytic electrodes. Each half-cell includes a passageway for feeding the respective gas to the corresponding microporous catalytic electrode.
    Type: Application
    Filed: May 16, 2002
    Publication date: January 2, 2003
    Applicant: STMicroelectronics S.r.l.
    Inventors: Giuseppe D'Arrigo, Salvatore Coffa, Rosario Corrado Spinella
  • Publication number: 20020185700
    Abstract: The high-gain photodetector is formed in a semiconductor-material body which houses a PN junction and a sensitive region that is doped with rare earths, for example erbium. The PN junction forms an acceleration and gain region separate from the sensitive region. The PN junction is reverse-biased and generates an extensive depletion region accommodating the sensitive region. Thereby, the incident photon having a frequency equal to the absorption frequency of the used rare earth crosses the PN junction, which is transparent to light, can be captured by an erbium ion in the sensitive region, so as to generate a primary electron, which is accelerated towards the PN junction by the electric field present, and can, in turn, generate secondary electrons by impact, according to an avalanche process. Thereby, a single photon can give rise to a cascade of electrons, thus considerably increasing detection efficiency.
    Type: Application
    Filed: May 8, 2002
    Publication date: December 12, 2002
    Applicant: STMicroelectronic S.r.l.
    Inventors: Salvatore Coffa, Sebania Libertino, Ferruccio Frisina
  • Publication number: 20020151100
    Abstract: Abstract of the Disclosure A monolithically integrated pressure sensor is produced through micromechanical surface structure definition techniques. A microphone cavity in the semiconductor substrate may be monolithically formed by plasma etching the front side or the back side of the silicon wafer to cut a plurality of trenches or holes deep enough to extend for at least part of its thickness into a doped buried layer of opposite type of conductivity of the substrate and of the epitaxial layer grown over it. The method may also include electrochemically etching through such trenches, the silicon of the buried layer with an electrolytic solution suitable for selectively etching the doped silicon of the opposite type of conductivity, thereby making the silicon of the buried layer porous. The method may also include oxidizing and leaching away the silicon so made porous.
    Type: Application
    Filed: December 11, 2001
    Publication date: October 17, 2002
    Applicant: STMicroelectronics S.r.l.
    Inventors: Salvatore Coffa, Luigi Occhipinti
  • Patent number: 6433399
    Abstract: An infrared detector device having a PN junction formed by a first semiconductor material region doped with rare earth ions and by a second semiconductor material region of opposite doping type. The detector device comprises a waveguide formed by a projecting structure extending on a substrate, including a reflecting layer and laterally delimited by a protection and containment oxide region. At least one portion of the waveguide is formed by the PN junction and has an end fed with light to be detected. The detector device has electrodes disposed laterally to and on the waveguide to enable efficient gathering of charge carriers generated by photoconversion.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: August 13, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventors: Albert Polman, Nicholas Hamelin, Peter Kik, Salvatore Coffa, Ferruccio Frisina, Mario Saggio
  • Publication number: 20020017657
    Abstract: A process for forming a thin layer of Silicon nanocrystals in an oxide layer is disclosed. The process includes, on a semiconductive substrate, thermally oxidizing a first portion of the substrate into an oxide layer, forming Silicon ions within the layer of oxide, and thermally treating the Silicon ions to become the thin layer of Silicon nanocrystals. In the inventive process the formation of the Silicon ions is by ionic implantation of the Silicon ions into the oxide at an ionization energy of between 0.1 keV and 7 keV, and preferably between 1 and 5 keV. This allows the Silicon atoms to coalesce in a lower temperature than would otherwise be possible. Additionally, more than one layer of nanocrystals can be formed by performing more than one implantation at more than one energy level. Embodiments of the invention can be used to form non-volatile memory devices with a very high quality having a very small size.
    Type: Application
    Filed: March 15, 2001
    Publication date: February 14, 2002
    Applicant: STMicroelectronics S.r.l.
    Inventors: Salvatore Coffa, Davide Patti
  • Publication number: 20010023094
    Abstract: A method for fabricating a silicon-on-insulator (SOI) wafer that includes a monocrystalline silicon substrate with a doped region buried therein is provided. The method includes forming a plurality of trench-like openings extending from a surface of the substrate to the doped buried region, and selectively etching through the plurality of trench-like openings to change the doped buried region into a porous silicon region. The porous silicon region is oxidized to obtain an insulating region for the SOI wafer.
    Type: Application
    Filed: December 29, 2000
    Publication date: September 20, 2001
    Applicant: STMicroelectronics S.r.l.
    Inventors: Giuseppe D'Arrigo, Corrado Spinella, Salvatore Coffa, Giuseppe Arena, Marco Camalleri
  • Patent number: 6168981
    Abstract: A method and apparatus for the localized reduction of the lifetime of charge carriers in integrated electronic devices. The method comprises the step of implanting ions, at a high dosage and at a high energy level, of a noble gas, preferably helium, in the active regions of the integrated device so that the ions form bubbles in the active regions. A further thermal treatment is performed after the formation of bubbles of the noble gas in order to improve the structure of the bubbles and to make the noble gas evaporate, leaving cavities in the active regions.
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: January 2, 2001
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Anna Battaglia, Piergiorgio Fallica, Cesare Ronsisvalle, Salvatore Coffa, Vito Raineri
  • Patent number: 5939769
    Abstract: There is described a bipolar power transistor with high breakdown voltage, obtained in a heavily doped semiconductor substrate of the N type, over which a lightly doped N type layer, constituting a collector region of the transistor, is superimposed. The transistor has a base region comprising a heavily doped P type diffusion, which extends into the lightly doped N type layer from a top surface. The transistor further includes an emitter region constituted by a heavily doped N type diffusion extending from the top surface within said heavily doped P type diffusion. The heavily doped P type diffusion is obtained within a deep lightly doped P type diffusion, extending from said top surface into the lightly doped N type layer and formed with acceptor impurities of aluminum atoms.
    Type: Grant
    Filed: July 31, 1997
    Date of Patent: August 17, 1999
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Ferruccio Frisina, Salvatore Coffa
  • Patent number: 5900652
    Abstract: A method and apparatus for the localized reduction of the lifetime of charge carriers in integrated electronic devices. The method comprises the step of implanting ions, at a high dosage and at a high energy level, of a noble gas, preferably helium, in the active regions of the integrated device so that the ions form bubbles in the active regions. A further thermal treatment is performed after the formation of bubbles of the noble gas in order to improve the structure of the bubbles and to make the noble gas evaporate, leaving cavities in the active regions.
    Type: Grant
    Filed: July 25, 1995
    Date of Patent: May 4, 1999
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Anna Battaglia, Piergiorgio Fallica, Cesare Ronsisvalle, Salvatore Coffa, Vito Raineri
  • Patent number: 5569612
    Abstract: There is described a bipolar power transistor with high breakdown voltage, obtained in a heavily doped semiconductor substrate of the N type, over which a lightly doped N type layer, constituting a collector region of the transistor, is superimposed. The transistor has a base region comprising a heavily doped P type diffusion, which extends into the lightly doped N type layer from a top surface. The transistor further includes an emitter region constituted by a heavily doped N type diffusion extending from the top surface within said heavily doped P type diffusion. The heavily doped P type diffusion is obtained within a deep lightly doped P type diffusion, extending from said top surface into the lightly doped N type layer and formed with acceptor impurities of aluminum atoms.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 29, 1996
    Assignee: Consorzio per la Ricerca sulla Microelettronica Nel Mezzogiorno
    Inventors: Ferruccio Frisina, Salvatore Coffa