Abstract: Resonant DC-DC converter control circuitry includes a feedback input, a differential integrator, a resonant voltage input, a first comparator, and a second comparator. The differential integrator includes a first input, a second input, a first output, and a second output. The first input is coupled to the feedback input. The second input is coupled to a ground terminal. The first comparator includes a first input coupled to the resonant voltage input, and a second input coupled to the first output of the differential integrator. The second comparator includes a first input coupled to the resonant voltage input, and a second input coupled to the second output of the differential integrator.

Abstract: In an example, a system comprises a boost power factor correction (PFC) converter that includes a thermistor, an inductor, and a transistor and a PFC controller coupled to a common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a terminal of the transistor. A first flip-flop is coupled to the comparator and to a control terminal of the transistor. A zero current detector is coupled to the inductor. A timer is coupled to the comparator and to the zero current detector. A second flip-flop is coupled to the timer and to the control terminal of the transistor. An AND gate is coupled to the first and second flip-flops. The circuit includes third and fourth flip flops.

Abstract: Embodiments include systems, methods, and apparatuses for controlling off-time during a burst mode in an LLC converter. In one embodiment, a circuit comprises an LLC converter having a primary side and a burst mode controller, the burst mode controller configured to monitor, on the primary side of the LLC converter, electrical current, and in response to a determination that the electrical current is below a first threshold, increase an off-time for switches in the LLC converter and in response to a determination that the electrical current is above a second threshold that is higher than the first threshold, decrease the off-time for the switches in the LLC converter.

Abstract: Circuits and methods for converting a current to an output voltage are disclosed herein. An embodiment of the circuit includes a first switch connected between a source of current and a first node and a second switch connected between the first node and a common voltage. The circuit also includes a first controller for controlling the state of the first switch and a second controller for controlling the state of the second switch. A capacitor is coupled to the first node; the voltage on the capacitor is the output voltage. When the second switch is open, the capacitor charges, and when the second switch is closed, the capacitor does not charge. The current flows through the primary inductance of a transformer.

Abstract: A switching converter controller includes: a control loop adapted to be coupled to an output terminal of a power stage; and a hybrid hysteretic control (HHC) circuit coupled to the control loop. The HHC circuit includes a resonant capacitor voltage (Vcr) node adapted to be coupled to a resonant capacitor (Cr) of the power stage, where the Vcr node sums a sense voltage for Cr with a frequency compensation ramp. The HHC circuit also includes a soft-start controller coupled to the Vcr node. The soft-start controller includes a clamp circuit coupled to the Vcr node.

Abstract: Resonant DC-DC converter control circuitry includes a feedback input, a differential integrator, a resonant voltage input, a first comparator, and a second comparator. The differential integrator includes a first input, a second input, a first output, and a second output. The first input is coupled to the feedback input. The second input is coupled to a ground terminal. The first comparator includes a first input coupled to the resonant voltage input, and a second input coupled to the first output of the differential integrator. The second comparator includes a first input coupled to the resonant voltage input, and a second input coupled to the second output of the differential integrator.

Abstract: A switching converter controller includes: a control loop adapted to be coupled to an output terminal of a power stage; and a hybrid hysteretic control (HHC) circuit coupled to the control loop. The HHC circuit includes a resonant capacitor voltage (Vcr) node adapted to be coupled to a resonant capacitor (Cr) of the power stage, where the Vcr node sums a sense voltage for Cr with a frequency compensation ramp. The HHC circuit also includes a soft-start controller coupled to the Vcr node. The soft-start controller includes a clamp circuit coupled to the Vcr node.

Abstract: Embodiments include systems, methods, and apparatuses for controlling off-time during a burst mode in an LLC converter. In one embodiment, a circuit comprises an LLC converter having a primary side and a burst mode controller, the burst mode controller configured to monitor, on the primary side of the LLC converter, electrical current, and in response to a determination that the electrical current is below a first threshold, increase an off-time for switches in the LLC converter and in response to a determination that the electrical current is above a second threshold that is higher than the first threshold, decrease the off-time for the switches in the LLC converter.

Abstract: In an example, a system comprises a boost power factor correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node. The system also comprises a PFC controller coupled to the common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a non-control terminal of the transistor; a first flip-flop coupled to the comparator and to a control terminal of the transistor; a zero current detector coupled to the inductor; a timer coupled to the comparator and to the zero current detector; a second flip-flop coupled to the timer and to the control terminal of the transistor; an AND gate coupled to the first and second flip-flops; a third flip-flop coupled to the second flip-flop and to the control terminal of the transistor; and a fourth flip-flop coupled to the AND gate and to the control terminal of the transistor.

Abstract: Embodiments include systems, methods, and apparatuses for controlling off-time during a burst mode in an LLC converter. In one embodiment, a circuit comprises an LLC converter having a primary side and a burst mode controller, the burst mode controller configured to monitor, on the primary side of the LLC converter, electrical current, and in response to a determination that the electrical current is below a first threshold, increase an off-time for switches in the LLC converter and in response to a determination that the electrical current is above a second threshold that is higher than the first threshold, decrease the off-time for the switches in the LLC converter.

Abstract: In an example, a system comprises a boost power factor correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node. The system also comprises a PFC controller coupled to the common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a non-control terminal of the transistor; a first flip-flop coupled to the comparator and to a control terminal of the transistor; a zero current detector coupled to the inductor; a timer coupled to the comparator and to the zero current detector; a second flip-flop coupled to the timer and to the control terminal of the transistor; an AND gate coupled to the first and second flip-flops; a third flip-flop coupled to the second flip-flop and to the control terminal of the transistor; and a fourth flip-flop coupled to the AND gate and to the control terminal of the transistor.

Abstract: In an example, a circuit includes a first power switch device coupled between a voltage input and an output terminal, the first power switch device having a control input. A voltage divider circuit includes a first resistor and a second resistor. The first resistor is coupled between the voltage input and a sense node between the first resistor and the second resistor. The second resistor has a first terminal coupled to the sense node and a second terminal. A second switch device is coupled between the second terminal of the second resistor and an electrical ground terminal. A voltage clamp is coupled between the sense node and the electrical ground terminal.

Abstract: In an example, a circuit includes a first power switch device coupled between a voltage input and an output terminal, the first power switch device having a control input. A voltage divider circuit includes a first resistor and a second resistor. The first resistor is coupled between the voltage input and a sense node between the first resistor and the second resistor. The second resistor has a first terminal coupled to the sense node and a second terminal. A second switch device is coupled between the second terminal of the second resistor and an electrical ground terminal. A voltage clamp is coupled between the sense node and the electrical ground terminal.

Abstract: A switch-mode power supply includes a power transistor, a transformer, and detection circuitry. The transformer includes a primary winding that is coupled to a drain terminal of the power transistor. The detection circuitry is coupled to a source terminal of the power transistor. The detection circuitry is operable to monitor signal present on the drain terminal via parasitic drain-source capacitance of the power transistor while the power transistor is switched off, and to detect demagnetization of a secondary winding of the transformer via the monitored signal.

Abstract: A power factor correction circuit includes a power transistor, an inductor, and detection circuitry. The inductor is coupled to a drain terminal of the power transistor. The detection circuitry is coupled to the drain terminal of the power transistor. The detection circuitry is configured to determine an input voltage applied to the inductor based on resonant ringing of voltage at the drain terminal, and to detect a valley in the voltage at the drain terminal based on the input voltage applied to the inductor.

Abstract: A power factor correction controller zero current detection circuit includes a differentiator circuit, a comparator, a first qualification timer circuit, an idle ringing detector circuit, a second qualification timer circuit, and a flip-flop. The comparator is coupled to the differentiator circuit. The first qualification timer circuit includes an input coupled to an output of the comparator. The idle ringing detector circuit includes a first input coupled to the output of the comparator, and a second input coupled to an output of the first qualification timer circuit. The second qualification timer circuit includes a first input coupled to the output of the first qualification timer circuit, and a second input coupled an output of the idle ringing detector circuit. The flip-flop includes a first input coupled to the output of the comparator, and a second input coupled to an output of the second qualification timer circuit.

Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.

Abstract: A power factor correction circuit includes a power transistor, an inductor, and detection circuitry. The inductor is coupled to a drain terminal of the power transistor. The detection circuitry is coupled to the drain terminal of the power transistor. The detection circuitry is configured to determine an input voltage applied to the inductor based on resonant ringing of voltage at the drain terminal, and to detect a valley in the voltage at the drain terminal based on the input voltage applied to the inductor.

Abstract: A power factor correction circuit includes a power transistor, an inductor, and detection circuitry. The inductor is coupled to a drain terminal of the power transistor. The detection circuitry is coupled to the drain terminal of the power transistor. The detection circuitry is configured to determine an input voltage applied to the inductor based on resonant ringing of voltage at the drain terminal, and to detect a valley in the voltage at the drain terminal based on the input voltage applied to the inductor.

Abstract: In an example, a system comprises a boost power factor correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node. The system also comprises a PFC controller coupled to the common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a non-control terminal of the transistor; a first flip-flop coupled to the comparator and to a control terminal of the transistor; a zero current detector coupled to the inductor; a timer coupled to the comparator and to the zero current detector; a second flip-flop coupled to the timer and to the control terminal of the transistor; an AND gate coupled to the first and second flip-flops; a third flip-flop coupled to the second flip-flop and to the control terminal of the transistor; and a fourth flip-flop coupled to the AND gate and to the control terminal of the transistor.