Abstract: A resistive structure integrated in a semiconductor substrate and having a suitably doped polysilicon region that is completely surrounded by a dielectric region so that the resistive structure is isolated electrically from other components jointly integrated in the semiconductor substrate.

Abstract: A vertical capacitor structure fabricated in a semiconductor substrate region overlaid by a buried oxide layer and a buried doped layer, as well as by a semiconductor layer that includes a sinker doped region in contact with the buried doped layer, wherein an oxide trench structure is formed, this oxide trench structure being filled with suitably doped polysilicon to produce, in combination with the sinker region, the plates of the vertical capacitor structure, with the oxide trench structure forming the dielectric therebetween. A process for integrating a vertical capacitor structure starting from a structure blank that includes a semiconductor substrate, a buried oxide layer and a buried doped layer is also provided.

Abstract: A monolithic integrated device includes a protection structure and is formed in a semiconductor material substrate having a first conductivity type, which device includes at least a first epitaxial layer formed on the substrate. The integrated device further includes a bipolar first transistor formed of a base region having a second conductivity type and including a first buried region formed in the first epitaxial layer, and having a first diffused region which extends from the first buried region to contact a top surface of the integrated device through a surface contact region with a high concentration of dopant material. The first transistor also has an emitter region with the first conductivity type, embedded in the base region, and including a second buried region formed on the first buried region and a second diffused region, with a high concentration of dopant material, which extends from the second buried region to contact the top surface of the integrated device.

Abstract: A vertical PNP transistor integrated in a semiconductor material wafer having an N type substrate and an N type epitaxial layer forming a surface. The transistor has a P type buried collector region astride the substrate and the epitaxial layer; a collector sinker insulating an epitaxial tub from the rest of the wafer; a gain-modulating N type buried base region astride the buried collector region and the epitaxial tub, and forming a base region with the epitaxial tub; and a P type emitter region in the epitaxial tub. An N.sup.+ type base sinker extends from the surface, through the epitaxial tub to the buried base region. The gain of the transistor may be modulated by varying the extension and dope concentration of the buried base region, forming a constant or variable dope concentration profile of the buried base region, providing or not a base sinker, and varying the form and distance of the base sinker from the emitter region.

Abstract: The invention relates to a control circuit for semiconductor devices which is formed on a substrate (1) doped by a first dopant type, the integrated circuit comprising a first epitaxial layer (2) grown on the substrate (1) and doped by the first dopant type, and an isolation well (3) doped by a second dopant type, the control circuit comprising at least a first control transistor (M1) formed in a first well (8) doped by the second dopant type and formed in the insulation well (3). Thus, the control circuit comprises at least one N-channel MOS transistor accommodated within a well in direct contact with the isolation well to eliminate a buried layer that, in prior art arrangements, involved the presence of an undesired parasitic component.

Abstract: A method of fabricating a junction-isolated semiconductor device is provided which includes the following steps. Within a first P-type buried region second N-type buried regions are formed. Over the first and second buried regions, an N-type epitaxial layer defining a surface of the device is grown. In the epitaxial layer, P-type isolation regions extending from the surface down to and in electric continuity with the first buried region and defining, with the first buried region, N-type wells incorporating the second buried regions is formed. And, P-type annular border regions in the epitaxial layer and to the side of the isolation regions are formed. The steps of forming isolation regions and annular border regions semiconducting regions being performed in a single step of selectively introducing doping ions.

Abstract: A power semiconductor structure (200), in particular in VIPower technology, made from a chip of N-type semiconductor material (110), comprising a bipolar or field-effect vertical power transistor (125, 120, 110) having a collector or drain region in such N-type material (110); the semiconductor structure comprises a PNP bipolar lateral power transistor (210, 110, 220) having a base region in such N-type material (110) substantially in common with the collector or drain region of the vertical power transistor.

Abstract: An integrated edge structure for a high voltage semiconductor device comprising a PN junction represented by a diffused region of a first conductivity type extending from a semiconductor device top surface is described. The edge structure comprises a first, lightly doped ring of the first conductivity type obtained in a first, lightly doped epitaxial layer of a second conductivity type and surrounding said diffused region, and a second, lightly doped ring of the first conductivity type, comprising at least one portion superimposed on and merged with said first ring, obtained in a second, lightly doped epitaxial layer of the second conductivity type grown over the first epitaxial layer.

Abstract: A monolithic semiconductor device having an edge structure that facilitates integrating high power devices an logic devices on the same substrate. The semiconductor device includes on a substrate of a first type of doping, a control region of a second type of doping, which is provided with an edge region, and a power region of a second type of doping. In the edge region, at least one channel is provided which is adapted to divide the edge region into regions that are electrically isolated from each other, the region at the channel being covered with a field plate. A method for producing such an edge structure in combination with the production execution of the monolithic device is also disclosed herein.

Abstract: A semiconductor device including a substrate having a first conductivity type on which are formed first and second epitaxial layers of the same conductivity type of the substrate. The semiconductor device also includes a first diffused region having a second conductivity type formed in a first portion of the first and second epitaxial layers. Said first diffused region defines a first junction with said first and second epitaxial layers. The semiconductor device also comprises an edge structure having the second conductivity type formed in a second portion of the first and second epitaxial layers. The edge structure includes a second diffused region having the second conductivity type formed in the first and second epitaxial layers, said second diffused region defining a second junction with said first and second epitaxial layers.

Abstract: The invention relates to a control circuit for semiconductor devices which is formed on a substrate (1) doped by a first dopant type, the integrated circuit comprising a first epitaxial layer (2) grown on the substrate (1) and doped by the first dopant type, and an isolation well (3) doped by a second dopant type, the control circuit comprising at least a first control transistor (M1) formed in a first well (8) doped by the second dopant type and formed in the insulation well (3). Thus, the control circuit comprises at least one N-channel MOS transistor accommodated within a well in direct contact with the isolation well to eliminate a buried layer that, in prior art arrangements, involved the presence of an undesired parasitic component.

Abstract: An integrated edge structure for a high voltage semiconductor device comprising a PN junction represented by a diffused region of a first conductivity type extending from a semiconductor device top surface is described. The edge structure comprises a first, lightly doped ring of the first conductivity type obtained in a first, lightly doped epitaxial layer of a second conductivity type and surrounding said diffused region, and a second, lightly doped ring of the first conductivity type, comprising at least one portion superimposed on and merged with said first ring, obtained in a second, lightly doped epitaxial layer of the second conductivity type grown over the first epitaxial layer.

Abstract: A damper for damping the vibration of blades in a turbine rotor including a plate having at least one bumper extending outwardly from one side of the plate to be positioned in recesses on the underside of the platforms on adjacent blades for locating the bumper circumferentially and with a tab extending inwardly from the plate on the side opposite to the bumper to hold the damper in radial position. A wear strip extending upwardly from the plate near its periphery serves as a seal to minimize gas leakage past the damper.

Abstract: A turbine wheel assembly having an improved blade attachment is disclosed. Techniques for increasing the low cycle fatigue life of the components forming the attachment are developed. In one specific embodiment a "fir tree" type attachment includes interlocking root teeth and disk teeth. Correspondingly, grooves accommodate the interlocking teeth. Each groove is contoured in a first region to a first radius and in a second region to a second radius.