Abstract: A method for generating a dual rate clock circuit the method including coupling the output terminal of a first local clock buffer to the input of a second local clock buffer through at least one inverter circuit and driving the first local clock buffer with a base signal. The method also includes generating an early clock signal with the first local clock buffer based on the base signal and generating a delayed early clock signal by delaying the first local clock signal with the at least one inverter. The method also includes generating a later clock signal by driving the second local clock buffer with the delayed early clock signal wherein the second local clock buffer and the late clock signal generated by the second local clock buffer are synchronized and correlated with the first local clock buffer and the early clock signal generated by the first local clock buffer.

Abstract: A method and apparatus implement improved timing performance of a signal bus through wire permutation with repowering buffers. A repowering buffer includes a prebuffer and a postbuffer. A plurality of prebuffers and postbuffers are stored in a design library, each having a set wiring ordered arrangement for selectively providing wire permutation of the signal bus. A wiring order of prebuffer at the beginning of the bus is identical to the wiring order of the postbuffer at the end of bus. The wiring order of the postbuffer driving the beginning of bus wires between adjacent repowering buffers is identical to the wiring order of the prebuffer receiving at the end of the bus wires. A wiring order of the downstream buffer pairs is chosen so that there is at least one pair of wires separated by another wire or wires in the bus.

Abstract: A method and apparatus are provided for implementing subthreshold leakage current reduction in limited switch dynamic logic (LSDL). A limited switch dynamic logic circuit includes a cross-coupled NAND and inverter logic. A dynamic node provides a first input to the NAND. A sleep signal provides a second input to the NAND. An output of the NAND provides an input to the inverter logic that inverts the NAND output and provides a complementary output. The NAND logic includes a series connected first sleep transistor receiving the sleep input. The first sleep transistor is turned OFF during the sleep mode. A second sleep transistor is connected between a voltage supply rail and the NAND output. The second sleep transistor is turned ON during the sleep mode to force high the NAND output and force low complementary output.

Abstract: An eFuse reference cell on a chip provides a reference voltage that is greater than a maximum voltage produced by an eFuse cell having an unblown eFuse on the chip but less than a minimum voltage produced by an eFuse cell having a blown eFuse on the chip. A reference current flows through a resistor and an unblown eFuse in the eFuse reference cell, producing the reference voltage. The reference voltage is used to create a mirrored copy of the reference current in the eFuse cell. The mirrored copy of the reference current flows through an eFuse in the eFuse cell. A comparator receives the reference voltage and the voltage produced by the eFuse cell. The comparator produces an output logic level responsive to the voltage produced by the eFuse cell compared to the reference voltage.

Abstract: A wireless data retrieval device and method for implementing the same. In accordance with one embodiment of the invention, the wireless data retrieval device includes a first-in-first-out (FIFO) memory queue in the form of a linked list that stores standardized correspondence information. The wireless data retrieval device further includes an input/output device configured to transmit the standardized correspondence information to and receive said standardized correspondence information from a wireless channel.

Abstract: A method and apparatus are described which periodically sense environmental conditions, such as temperature, humidity, or voltage applied to a product, and apply these sensed measurements to models of ageing acceleration. Acceleration factors from the models are accumulated in nonvolatile storage. The accumulated effective aging of the product is displayed to the owner or prospective customer in various desired formats, such as effective age, current acceleration factor, estimate of effective life used, or estimate of remaining life left in the product. A warning can be sent to the user to indicate that the product's effective life is over or is nearly over.

Abstract: A flex cable has a number of conductive wirings for electrically coupling electrical leads of an electrical component to a wiring board. The flex cable has a conductive tab for electrically coupling one of the conductive wirings to one of the leads. The flex cable is bendable to form an essentially horizontal portion and an essentially vertical portion. The conductive tab is disposed at a transition between the horizontal portion and the vertical portion.

Abstract: A flex cable has a number of conductive wirings for electrically coupling electrical leads of an electrical component to a wiring board. The flex cable has a conductive tab for electrically coupling one of the conductive wirings to one of the leads. The flex cable is bendable to form an essentially horizontal portion and an essentially vertical portion. The conductive tab is disposed at a transition between the horizontal portion and the vertical portion.

Abstract: A method and apparatus are described which periodically sense environmental conditions, such as temperature, humidity, or voltage applied to a product, and apply these sensed measurements to models of ageing acceleration. Acceleration factors from the models are accumulated in nonvolatile storage. The accumulated effective aging of the product is displayed to the owner or prospective customer in various desired formats, such as effective age, current acceleration factor, estimate of effective life used, or estimate of remaining life left in the product. A warning can be sent to the user to indicate that the product's effective life is over or is nearly over.

Abstract: A wireless data retrieval device and method for implementing the same. In accordance with one embodiment of the invention, the wireless data retrieval device includes a first-in-first-out (FIFO) memory queue in the form of a linked list that stores standardized correspondence information. The wireless data retrieval device further includes an input/output device configured to transmit the standardized correspondence information to and receive said standardized correspondence information from a wireless channel.

Abstract: A device and method for verifying independent reads and writes in a memory array includes bit inserters in the array to simultaneously insert a predetermined value into multiple portions of the array. Each row may have a corresponding row bit inserter. Alternatively, or in addition, each memory cell may have a storage element bit inserter. A row bit inserter places a predetermined value at the inputs of a row write port. The storage element bit inserters pre-set memory cells to a predetermined value. To test the read circuitry, storage element bit inserters are set to a predetermined value, and a read is performed. If the value read from a memory cell does not match the value to which it was set, it can be inferred that the read circuitry is not functioning properly. If the values match, it can be inferred that the read circuitry is functioning properly. To test the write circuitry, a row bit inserter may be set to a predetermined value. A write is performed, followed by a read.

Abstract: A multi-threaded memory (and associated method) for use in a multi-threaded computer system in which plural threads are used with a single processor. The multi-threaded memory includes: multi-threaded storage cells; at least one write decoder supplying information to a selected multi-threaded storage cell; and at least one read decoder accessing information from a selected multi-threaded storage cell. Each of the multi-threaded storage cells includes: N storage elements, where N.gtoreq.2, each of the N storage elements having a thread-correspondent content; a write interface supplying information to the intra-cell storage elements; and a read interface reading information from the intra-cell storage elements. At least one of the intra-cell read and write interfaces selects one of the thread-correspondent contents based at least in part by identifying the corresponding thread to achieve intra-cell thread-correspondent content selection.