Patents by Inventor Salvatore Nickolas Storino

Salvatore Nickolas Storino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of testing susceptibility to failure of functional circuitry embodied in an integrated circuit
    Patent number: 6111422
    Abstract: A test device is formed on a chip which allows the susceptibility to failure of functional circuitry formed on the chip to be tested. The test device allows aggressive design of chips which include sensitive circuitry, such as precharged dynamic logic, by testing whether deviations from the design specification introduced during manufacturing of the chip are sufficient to cause failure of the functional circuitry.
    Type: Grant
    Filed: April 30, 1999
    Date of Patent: August 29, 2000
    Assignee: International Business Machines Corporation
    Inventors: Salvatore Nickolas Storino, Robert Russell Williams
  • Semiconductor device having embedded test device for testing design specifications
    Patent number: 6049218
    Abstract: A test device is formed on a chip which allows the susceptibility to failure of functional circuitry formed on the chip to be tested. The test device allows aggressive design of chips which include sensitive circuitry, such as precharged dynamic logic, by testing whether deviations from the design specification introduced during manufacturing of the chip are sufficient to cause failure of the functional circuitry.
    Type: Grant
    Filed: April 17, 1998
    Date of Patent: April 11, 2000
    Assignee: International Business Machines Corporation
    Inventors: Salvatore Nickolas Storino, Robert Russell Williams
  • Test device and method facilitating aggressive circuit design
    Patent number: 6005406
    Abstract: A test device is formed on a chip which allows the susceptibility to failure of functional circuitry formed on the chip to be tested. The test device allows aggressive design of chips which include sensitive circuitry, such as precharged dynamic logic, by testing whether deviations from the design specification introduced during manufacturing of the chip are sufficient to cause failure of the functional circuitry.
    Type: Grant
    Filed: December 7, 1995
    Date of Patent: December 21, 1999
    Assignee: International Business Machines Corporation
    Inventors: Salvatore Nickolas Storino, Robert Russell Williams