Patents by Inventor Salvatore Nicosia
Salvatore Nicosia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6801466Abstract: A circuit for controlling a reference node in a sense amplifier switchable between an operating mode and a stand-by mode is provided. The reference node provides a reference voltage in the operating mode. The circuit may include circuitry for bringing the reference node to a starting voltage upon entry into the stand-by mode, circuitry for keeping the reference node at a pre-charging voltage in the stand-by mode, and circuitry for providing a comparison voltage closer to the pre-charging voltage than the starting voltage. Pulling circuitry may also be included for pulling the reference node toward a power supply voltage. Further, a controller may activate the pulling circuitry upon entering the stand-by mode, and disable the pulling circuitry when the voltage at the reference node reaches the comparison voltage.Type: GrantFiled: December 27, 2002Date of Patent: October 5, 2004Assignee: STMicroelectronics S.r.l.Inventors: Salvatore Giove, Luca De Ambroggi, Salvatore Nicosia, Francesco Tomaiulo, Kumar Promod, Giuseppe Piazza, Francesco Pipitone
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Patent number: 6701419Abstract: A multipurpose interlaced memory device functions in two different modes, synchronous and asynchronous. The memory uses a circuit for detecting address transitions by acting as a synchronous clock of the system for letting the control circuit of the memory device recognize the required access mode by enabling a comparison of the currently input external address with the one stored in the address counters of the two banks of memory cells. The memory device includes a buffer for outputting data. The buffer includes a circuit for pre-charging the output nodes to an intermediate voltage between the voltages corresponding to the two possible logic states, thus reducing noise and improving transfer time.Type: GrantFiled: October 15, 2001Date of Patent: March 2, 2004Assignee: STMicroelectronics S.r.l.Inventors: Francesco Tomaiuolo, Salvatore Nicosia, Luigi Pascucci
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Patent number: 6625706Abstract: A method of synchronizing the start of sequential read cycles when reading data in a memory in a synchronous mode with sequential access uses the increment pulses as synchronization signals for the address counters of the memory cell array. Following each increment pulse, a dummy ATD pulse is generated. The dummy ATD pulse is undistinguishable from an ATD pulse generated upon detection of a switching of external address lines.Type: GrantFiled: January 31, 2001Date of Patent: September 23, 2003Assignee: STMicroelectronics S.r.l.Inventors: Fabrizio Campanale, Salvatore Nicosia, Francesco Tomaiuolo, Luca Giuseppe De Ambroggi, Promod Kumar
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Patent number: 6624679Abstract: A delay circuit includes a first inverter connected to a supply voltage, and has an input for receiving an input signal. A delay regulating transistor is connected between the first inverter and a first voltage reference, and has a control terminal for receiving a biasing voltage. A capacitor is connected between an output of the first inverter and the first voltage reference. A second inverter is connected to the output of the first inverter for outputting a delayed output signal. An auxiliary current path is in parallel to the delay regulating transistor for allowing a portion of a discharge current from the capacitor to flow therethrough. The portion of the discharge current is proportional to the supply voltage. The auxiliary current path includes a diode connected to the first inverter, and a second transistor connected between the diode and the first voltage reference. The second transistor has a control terminal for receiving the biasing voltage.Type: GrantFiled: January 31, 2001Date of Patent: September 23, 2003Assignee: STMicroelectronics S.r.l.Inventors: Francesco Tomaiuolo, Fabrizio Campanale, Salvatore Nicosia, Luca Giuseppe De Ambroggi, Promod Kumar
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Publication number: 20030142568Abstract: A circuit for controlling a reference node in a sense amplifier switchable between an operating mode and a stand-by mode is provided. The reference node provides a reference voltage in the operating mode. The circuit may include circuitry for bringing the reference node to a starting voltage upon entry into the stand-by mode, circuitry for keeping the reference node at a pre-charging voltage in the stand-by mode, and circuitry for providing a comparison voltage closer to the pre-charging voltage than the starting voltage. Pulling circuitry may also be included for pulling the reference node toward a power supply voltage. Further, a controller may activate the pulling circuitry upon entering the stand-by mode, and disable the pulling circuitry when the voltage at the reference node reaches the comparison voltage.Type: ApplicationFiled: December 27, 2002Publication date: July 31, 2003Applicant: STMicroelectronics S.r.I.Inventors: Salvatore Giove, Luca De Ambroggi, Salvatore Nicosia, Francesco Tomaiulo, Kumar Promod, Giuseppe Piazza, Francesco Pipitone
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Patent number: 6587913Abstract: A multipurpose memory device suitable for a broader range of applications, whether requiring the reading of data in an asynchronous mode with random access (as in a standard memory) or in a synchronous sequential mode with sequential or burst type access, is capable of recognizing the mode of access and the mode of reading that is currently required by the microprocessor. The memory device self-conditions its internal circuitry as a function of such a recognition in order to read data in the requested mode without requiring the use of additional external control signals and/or implying a penalization in terms of access time and reading time compared to those which, for the same fabrication technology and state of the art design, may be attained with memory devices specifically designed for either one or the other mode of operation.Type: GrantFiled: January 31, 2001Date of Patent: July 1, 2003Assignee: STMicroelectronics S.r.l.Inventors: Fabrizio Campanale, Salvatore Nicosia, Francesco Tomaiuolo, Luca Giuseppe De Ambroggi, Promod Kumar, Luigi Pascucci
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Patent number: 6487140Abstract: A control circuit manages transferring of data within a system, such as an interleaved memory. The system includes a plurality of data sources for providing an output data stream synchronous with an external timing signal, an output register for storing data available at an output of the system, and a selection multiplexer for transferring the data from the plurality of data sources to the output register. The control circuit includes a plurality of circuit blocks, with each circuit block being dedicated to one of the plurality of data sources. Each circuit block includes a detection circuit for detecting availability of the data at an output of a selected data source, and a conditioned update path connected to the detection circuit provides an update flag. A logic gate having a first input receives the update flag and a second input receives an output signal from the detection circuit for providing a selection signal for the selection multiplexer.Type: GrantFiled: January 31, 2001Date of Patent: November 26, 2002Assignee: STMicroelectronics S.r.l.Inventors: Francesco Tomaiuolo, Fabrizio Campanale, Salvatore Nicosia, Luca Giuseppe De Ambroggi, Promod Kumar
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Patent number: 6473339Abstract: A redundancy architecture for a memory includes an array of memory cells divided into at least a pair of semi-arrays that are singularly addressable. Each semi-array is organized into rows and columns. The redundancy architecture includes a number of packets each including redundancy columns. The packets are divided into two subsets of packets. Each packet is addressable independently from the other by respective address circuits. Each packet also provides redundancy columns exclusively for a respective semi-array.Type: GrantFiled: January 31, 2001Date of Patent: October 29, 2002Assignee: STMicroelectronics S.r.l.Inventors: Luca Giuseppe De Ambroggi, Fabrizio Campanale, Salvatore Nicosia, Francesco Tomaiuolo, Promod Kumar
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Patent number: 6470431Abstract: An interleaved memory having an interleaved data path includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells, first and second arrays of sense amplifiers respectively coupled to the first and second bank of memory cells, and first and second read registers respectively coupled to the first and second arrays of sense amplifiers. A control and timing circuit is connected to the first and second arrays of sense amplifiers and has inputs for receiving externally generated command signals, and outputs for providing path selection signals and a control signal. A third register is connected to the first and second read registers and has inputs for receiving read data therein as a function of the path selection signals. An array of pass-gates are connected to the third register and are controlled in common by the control signal for enabling a transfer of the read data stored in the third register to an array of output buffers.Type: GrantFiled: January 31, 2001Date of Patent: October 22, 2002Assignee: STMicroelectronics S.r.l.Inventors: Salvatore Nicosia, Francesco Tomaiuolo, Fabrizio Campanale, Luca Giuseppe De Ambroggi, Promod Kumar
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Patent number: 6469566Abstract: A pre-charging circuit for the output node of an output buffer of an integrated digital system generates a first pulse for enabling the output of new data and a second pulse having a shorter duration than the first pulse for loading the new data in an output data register. The output data register is coupled to the input of the output buffer. A capacitor is connected in parallel to the load capacitance of the output node of the buffer by a pass-gate. The pass-gate is enabled by a pre-charge command corresponding to the logic AND of the second pulse and of the logic XOR of the new data and the data currently present on the output node. A driver is disabled by the first pulse for charging the capacitor to a voltage corresponding to the logic level of data belonging to the group that includes the new data and a logic inversion of the current data.Type: GrantFiled: January 31, 2001Date of Patent: October 22, 2002Assignee: STMicroelectronics S.r.l.Inventor: Salvatore Nicosia
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Publication number: 20020135413Abstract: A delay circuit includes a first inverter connected to a supply voltage, and has an input for receiving an input signal. A delay regulating transistor is connected between the first inverter and a first voltage reference, and has a control terminal for receiving a biasing voltage. A capacitor is connected between an output of the first inverter and the first voltage reference. A second inverter is connected to the output of the first inverter for outputting a delayed output signal. An auxiliary current path is in parallel to the delay regulating transistor for allowing a portion of a discharge current from the capacitor to flow therethrough. The portion of the discharge current is proportional to the supply voltage. The auxiliary current path includes a diode connected to the first inverter, and a second transistor connected between the diode and the first voltage reference. The second transistor has a control terminal for receiving the biasing voltage.Type: ApplicationFiled: January 31, 2001Publication date: September 26, 2002Applicant: STMincroelectronics S.r.I.Inventors: Francesco Tomaiuolo, Fabrizio Campanale, Salvatore Nicosia, Luca Giuseppe De Ambroggi, Promod Kumar
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Interleaved memory device for sequential access synchronous reading with simplified address counters
Patent number: 6452864Abstract: An interleaved memory includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells. The interleaved memory operates in a burst access mode. A first address counter is coupled to the first bank of memory cells, and an address register is coupled to the first address counter and to the second bank of memory cells. A timing circuit generates increment pulses to the first address counter so that a first random access asynchronous read cycle starts with the first bank of memory cells. A function of an address counter for the second bank of memory cells is being performed by coping contents of the first address counter to the address register.Type: GrantFiled: January 31, 2001Date of Patent: September 17, 2002Assignee: STMicroelectonics S.R.L.Inventors: Carmelo Condemi, Fabrizio Campanale, Salvatore Nicosia, Francesco Tomaiuolo, Luca Giuseppe De Ambroggi, Promod Kumar -
INTERLEAVED MEMORY DEVICE FOR SEQUENTIAL ACCESS SYNCHRONOUS READING WITH SIMPLIFIED ADDRESS COUNTERS
Publication number: 20020126563Abstract: An interleaved memory includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells. The interleaved memory operates in a burst access mode. A first address counter is coupled to the first bank of memory cells, and an address register is coupled to the first address counter and to the second bank of memory cells. A timing circuit generates increment pulses to the first address counter so that a first random access asynchronous read cycle starts with the first bank of memory cells. A function of an address counter for the second bank of memory cells is being performed by coping contents of the first address counter to the address register.Type: ApplicationFiled: January 31, 2001Publication date: September 12, 2002Applicant: STMicroelectronics S.r.l.Inventors: Carmelo Condemi, Fabrizio Campanale, Salvatore Nicosia, Francesco Tomaiuolo, Luca Giuseppe De Ambroggi, Promod Kumar -
Publication number: 20020087817Abstract: A multipurpose interlaced memory device functions in two different modes, synchronous and asynchronous. The memory uses a circuit for detecting address transitions by acting as a synchronous clock of the system for letting the control circuit of the memory device recognize the required access mode by enabling a comparison of the currently input external address with the one stored in the address counters of the two banks of memory cells. The memory device includes a buffer for outputting data. The buffer includes a circuit for pre-charging the output nodes to an intermediate voltage between the voltages corresponding to the two possible logic states, thus reducing noise and improving transfer time.Type: ApplicationFiled: October 15, 2001Publication date: July 4, 2002Applicant: STMicroelectronics S.r.I.Inventors: Francesco Tomaiuolo, Salvatore Nicosia, Luigi Pascucci
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Patent number: 6366634Abstract: An address binary counter for an interleaved having an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells includes as many stages as the bits that may be stored in the memory cells of a row of one of the banks, and a carry calculation network. The interleaved memory operates in a burst access mode enabled by an enabling signal. The carry calculation network includes an ordered group of independent carry generators. Each independent carry generator includes a certain number of stages, with each stage having inputs receiving its own enabling bit and a number of consecutive bits of a row of the bank equal to the number of stages, orderly starting from the least significant bit. The enabling bit of the first carry generator of the ordered group is the enabling signal, and the enabling bit of any other carry generator of the ordered group is the logic AND of the enabling signal and of the input bits of the preceding carry generator of the ordered group.Type: GrantFiled: January 31, 2001Date of Patent: April 2, 2002Assignee: STMicroelectronics S.R.L.Inventors: Luca Giuseppe De Ambroggi, Salvatore Nicosia, Francesco Tomaiuolo, Fabrizio Campanale, Promod Kumar, Carmelo Condemi
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Patent number: 6356505Abstract: An interleaved memory is readable in a sequential access synchronous mode and in a random access asynchronous mode based upon externally generated command signals including an address latch enabling signal and a chip enable signal. The memory includes a circuit for regenerating the externally generated address latch enabling signal. A first and a second internal replica signal are generated by the circuit. The second internal replica signal has a leading edge that is delayed with respect to a leading edge of the first internal replica signal. A duration of the second internal replica signal is conditionally incremented to prevent non-synchronization between the externally generated address latch enabling signal and the externally generated chip enable signal when the interleaved memory is operating in the sequential access synchronous mode or in the random access asynchronous mode.Type: GrantFiled: January 31, 2001Date of Patent: March 12, 2002Assignee: STMicroelectronics S.r.l.Inventors: Salvatore Nicosia, Fabrizio Campanale, Francesco Tomaiuolo, Luca Giuseppe De Ambroggi, Luigi Pascucci
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Publication number: 20010036244Abstract: An address binary counter for an interleaved having an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells includes as many stages as the bits that may be stored in the memory cells of a row of one of the banks, and a carry calculation network. The interleaved memory operates in a burst access mode enabled by an enabling signal. The carry calculation network includes an ordered group of independent carry generators. Each independent carry generator includes a certain number of stages, with each stage having inputs receiving its own enabling bit and a number of consecutive bits of a row of the bank equal to the number of stages, orderly starting from the least significant bit. The enabling bit of the first carry generator of the ordered group is the enabling signal, and the enabling bit of any other carry generator of the ordered group is the logic AND of the enabling signal and of the input bits of the preceding carry generator of the ordered group.Type: ApplicationFiled: January 31, 2001Publication date: November 1, 2001Applicant: STMicroelectronics S.r.l.Inventors: Luca Giuseppe De Ambroggi, Salvatore Nicosia, Francesco Tomaiuolo, Fabrizio Campanale, Promod Kumar, Carmelo Condemi
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Publication number: 20010035786Abstract: A pre-charging circuit for the output node of an output buffer of an integrated digital system generates a first pulse for enabling the output of new data and a second pulse having a shorter duration than the first pulse for loading the new data in an output data register. The output data register is coupled to the input of the output buffer. A capacitor is connected in parallel to the load capacitance of the output node of the buffer by a pass-gate. The pass-gate is enabled by a pre-charge command corresponding to the logic AND of the second pulse and of the logic XOR of the new data and the data currently present on the output node. A driver is disabled by the first pulse for charging the capacitor to a voltage corresponding to the logic level of data belonging to the group that includes the new data and a logic inversion of the current data.Type: ApplicationFiled: January 31, 2001Publication date: November 1, 2001Applicant: STMicroelectronics S.r.l.Inventor: Salvatore Nicosia
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Publication number: 20010036121Abstract: An interleaved memory is readable in a sequential access synchronous mode and in a random access asynchronous mode based upon externally generated command signals including an address latch enabling signal and a chip enable signal. The memory includes a circuit for regenerating the externally generated address latch enabling signal. A first and a second internal replica signal are generated by the circuit. The second internal replica signal has a leading edge that is delayed with respect to a leading edge of the first internal replica signal. A duration of the second internal replica signal is conditionally incremented to prevent non-synchronization between the externally generated address latch enabling signal and the externally generated chip enable signal when the interleaved memory is operating in the sequential access synchronous mode or in the random access asynchronous mode.Type: ApplicationFiled: January 31, 2001Publication date: November 1, 2001Applicant: STMicroelectronics S.r.l.Inventors: Salvatore Nicosia, Fabrizio Campanale, Francesco Tomaiuolo, Luca Giuseppe De Ambroggi, Luigi Pascucci
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Publication number: 20010034819Abstract: An interleaved memory having an interleaved data path includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells, first and second arrays of sense amplifiers respectively coupled to the first and second bank of memory cells, and first and second read registers respectively coupled to the first and second arrays of sense amplifiers. A control and timing circuit is connected to the first and second arrays of sense amplifiers and has inputs for receiving externally generated command signals, and outputs for providing path selection signals and a control signal. A third register is connected to the first and second read registers and has inputs for receiving read data therein as a function of the path selection signals. An array of pass-gates are connected to the third register and are controlled in common by the control signal for enabling a transfer of the read data stored in the third register to an array of output buffers.Type: ApplicationFiled: January 31, 2001Publication date: October 25, 2001Applicant: STMicroelectronics S.r.I.Inventors: Salvatore Nicosia, Francesco Tomaiuolo, Fabrizio Campanale, Luca Giuseppe De Ambroggi, Promod Kumar