Patents by Inventor Salvatore Pontarelli

Salvatore Pontarelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10171419
    Abstract: A data packet is received in a network element. The network element has a cache memory in which cache entries represent a portion of addresses stored in a main memory, The destination address and the cache entries each comprise a binary number. A first determination is made that a number M of the most significant bits of a cache entry and the destination address are identical. A second determination is made that an additional number M+L of the most significant bits of a cache entry and the destination address are identical. Routing information is then retrieved the cache memory, and the packet processed according to the routing information.
    Type: Grant
    Filed: June 19, 2016
    Date of Patent: January 1, 2019
    Assignee: Mellanox Technologies TLC Ltd.
    Inventors: Fima Kravchik, Pedro Reviriego, Salvatore Pontarelli, Aviv Kfir, Amir Roitshtein, Gil Levy
  • Patent number: 10148571
    Abstract: A routing table is represented as a binary search tree ordered by prefix lengths. Markers are placed to guide accessing nodes in designated subtrees to search for a longest prefix match with destination addresses of data packet. Destination descendant nodes in remote hierarchical levels of the tree are associated with the markers. The traversal of the binary search tree is conducted by accessing the respective destination descendant nodes while avoiding accessing nodes in intermediate hierarchical levels. The packet is processed using the longest prefix match.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: December 4, 2018
    Assignee: MELLANOX TECHNOLOGIES TLV LTD.
    Inventors: Aviv Kfir, Pedro Reviriego, Salvatore Pontarelli, Gil Levy
  • Publication number: 20180278525
    Abstract: In a network element cache operation is enhanced by extracting a set of fields from a packet, constructing a hash key from the extracted fields, and identifying a subset of the fields, wherein the field values thereof fail to exist in a set of classification rules. The hash key by is modified by masking the subset of the extracted fields. A hash lookup is performed using the modified hash key in a cache memory that stores a portion of the classification rules. The packet is processed responsively to the lookup.
    Type: Application
    Filed: March 26, 2017
    Publication date: September 27, 2018
    Inventors: Gil Levy, Pedro Reviriego, Salvatore Pontarelli, Aviv Kfir
  • Patent number: 10068034
    Abstract: A method includes extracting classification keys from a collection of data items. A corpus of rules for matching to the classification keys is received, each rule including a respective set of unmasked bits having corresponding bit values, and at least some of the rules also include masked bits. Rule patterns are extracted from the corpus, each rule pattern defining a respective sequence of masked and unmasked bits to which one or more of the rules conforms. Multiple hash tables are defined in a RAM, each is used for searching for a rule that matches a given classification key. A match result of a given rule in a given hash table is also indicative of which of the other hash tables are to be used for subsequent searching. The data items are classified by matching the respective classification keys to the rules using one or more of the hash tables.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: September 4, 2018
    Assignee: Mellanox Technologies TLV Ltd.
    Inventors: Gil Levy, Pedro Reviriego, Salvatore Pontarelli
  • Patent number: 10049126
    Abstract: Decision apparatus includes a first memory bank, containing a first table of hash composition factors, and a second memory bank, containing second and third tables of associative entries. A logic pipeline receives a sequence of data items and extracts a search key from each data item. A pre-hash circuit computes a first index by applying a first hash function to the search key. A first lookup circuit reads a hash composition factor from a location in the first memory bank indicated by the first index, and a hash circuit compute second and third indices as different combinations, determined by the hash composition factor, of second and third hash functions applied by the hash circuit to the search key. A second lookup circuit reads the entries in the second and third tables that are indicated respectively by the second and third indices.
    Type: Grant
    Filed: September 6, 2015
    Date of Patent: August 14, 2018
    Assignee: MELLANOX TECHNOLOGIES TLV LTD.
    Inventors: Gil Levy, Pedro Reviriego, Salvatore Pontarelli
  • Patent number: 9984144
    Abstract: A method for classification includes extracting respective classification keys from a collection of data items and receiving a corpus of rules for matching to the classification keys. At least some of the rules include masked bits in addition to the unmasked bits. Rule patterns are extracted from the corpus, defining different, respective sequences of masked and unmasked bits to which one or more of the rules conform. The rule patterns are grouped into extended rule patterns, such that the respective set of unmasked bits in any rule pattern is a superset of the unmasked bits in the extended rule pattern into which it is grouped. Rule entries corresponding to the rules are computed using the extended rule patterns and are stored in a random access memory (RAM). The data items are classified by matching the respective classification keys to the rule entries in the RAM.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: May 29, 2018
    Assignee: MELLANOX TECHNOLOGIES TLV LTD.
    Inventors: Gil Levy, Pedro Reviriego, Salvatore Pontarelli
  • Publication number: 20180068032
    Abstract: A method includes extracting classification keys from a collection of data items. A corpus of rules for matching to the classification keys is received, each rule including a respective set of unmasked bits having corresponding bit values, and at least some of the rules also include masked bits. Rule patterns are extracted from the corpus, each rule pattern defining a respective sequence of masked and unmasked bits to which one or more of the rules conforms. Multiple hash tables are defined in a RAM, each is used for searching for a rule that matches a given classification key. A match result of a given rule in a given hash table is also indicative of which of the other hash tables are to be used for subsequent searching. The data items are classified by matching the respective classification keys to the rules using one or more of the hash tables.
    Type: Application
    Filed: September 7, 2016
    Publication date: March 8, 2018
    Inventors: Gil Levy, Pedro Reviriego, Salvatore Pontarelli
  • Patent number: 9892057
    Abstract: In a network element a decision apparatus has a plurality of multi-way hash tables of single size and double size associative entries. A logic pipeline extracts a search key from each of a sequence of received data items. A hash circuit applies first and second hash functions to the search key to generate first and second indices. A lookup circuit reads associative entries in the hash tables that are indicated respectively by the first and second indices, matches the search key against the associative entries in all the ways. Upon finding a match between the search key and an entry key in an indicated associative entry. A processor uses the value of the indicated associative entry to insert associative entries from a stash of associative entries into the hash tables in accordance with a single size and a double size cuckoo insertion procedure.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: February 13, 2018
    Assignee: MELLANOX TECHNOLOGIES TLV LTD.
    Inventors: Gil Levy, Salvatore Pontarelli, Pedro Reviriego
  • Publication number: 20170366502
    Abstract: A data packet is received in a network element. The network element has a cache memory in which cache entries represent a portion of addresses stored in a main memory, The destination address and the cache entries each comprise a binary number. A first determination is made that a number M of the most significant bits of a cache entry and the destination address are identical. A second determination is made that an additional number M+L of the most significant bits of a cache entry and the destination address are identical. Routing information is then retrieved the cache memory, and the packet processed according to the routing information.
    Type: Application
    Filed: June 19, 2016
    Publication date: December 21, 2017
    Inventors: Fima Kravchik, Pedro Reviriego, Salvatore Pontarelli, Aviv Kfir, Amir Roitshtein, Gil Levy
  • Publication number: 20170366459
    Abstract: A routing table is represented as a binary search tree ordered by prefix lengths. Markers are placed to guide accessing nodes in designated subtrees to search for a longest prefix match with destination addresses of data packet. Destination descendant nodes in remote hierarchical levels of the tree are associated with the markers. The traversal of the binary search tree is conducted by accessing the respective destination descendant nodes while avoiding accessing nodes in intermediate hierarchical levels. The packet is processed using the longest prefix match.
    Type: Application
    Filed: June 20, 2016
    Publication date: December 21, 2017
    Inventors: Aviv Kfir, Pedro Reviriego, Salvatore Pontarelli, Gil Levy
  • Publication number: 20170286292
    Abstract: In a network element a decision apparatus has a plurality of multi-way hash tables of single size and double size associative entries. A logic pipeline extracts a search key from each of a sequence of received data items. A hash circuit applies first and second hash functions to the search key to generate first and second indices. A lookup circuit reads associative entries in the hash tables that are indicated respectively by the first and second indices, matches the search key against the associative entries in all the ways. Upon finding a match between the search key and an entry key in an indicated associative entry. A processor uses the value of the indicated associative entry to insert associative entries from a stash of associative entries into the hash tables in accordance with a single size and a double size cuckoo insertion procedure.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Inventors: Gil Levy, Salvatore Pontarelli, Pedro Reviriego
  • Publication number: 20170068669
    Abstract: Decision apparatus includes a first memory bank, containing a first table of hash composition factors, and a second memory bank, containing second and third tables of associative entries. A logic pipeline receives a sequence of data items and extracts a search key from each data item. A pre-hash circuit computes a first index by applying a first hash function to the search key. A first lookup circuit reads a hash composition factor from a location in the first memory bank indicated by the first index, and a hash circuit compute second and third indices as different combinations, determined by the hash composition factor, of second and third hash functions applied by the hash circuit to the search key. A second lookup circuit reads the entries in the second and third tables that are indicated respectively by the second and third indices.
    Type: Application
    Filed: September 6, 2015
    Publication date: March 9, 2017
    Inventors: Gil Levy, Pedro Reviriego, Salvatore Pontarelli
  • Publication number: 20170052731
    Abstract: A method for classification includes extracting respective classification keys from a collection of data items and receiving a corpus of rules for matching to the classification keys. At least some of the rules include masked bits in addition to the unmasked bits. Rule patterns are extracted from the corpus, defining different, respective sequences of masked and unmasked bits to which one or more of the rules conform. The rule patterns are grouped into extended rule patterns, such that the respective set of unmasked bits in any rule pattern is a superset of the unmasked bits in the extended rule pattern into which it is grouped. Rule entries corresponding to the rules are computed using the extended rule patterns and are stored in a random access memory (RAM). The data items are classified by matching the respective classification keys to the rule entries in the RAM.
    Type: Application
    Filed: August 17, 2015
    Publication date: February 23, 2017
    Inventors: Gil Levy, Pedro Reviriego, Salvatore Pontarelli
  • Publication number: 20170053012
    Abstract: A method for classification includes extracting respective classification keys from a collection of data items and defining a set of patterns for matching to the classification keys. A plurality of memory banks contain respective Bloom filters, each Bloom configured to indicate one or more patterns in the set that are candidates to match a given classification key. A respective first hash function is applied to the classification keys for each pattern in order to select, for each classification key, one of the Bloom filters to query for the pattern. The selected Bloom filters are queried by applying a respective second hash function to each classification key, so as to receive from the Bloom filters an indication of the one or more candidate patterns. The data items are classified by matching the respective classification keys against the candidate patterns.
    Type: Application
    Filed: August 17, 2015
    Publication date: February 23, 2017
    Inventors: Gil Levy, Pedro Reviriego, Salvatore Pontarelli, Efim Yehiel Kravchik