Abstract: A DRAM has an input address buffer in which the first stage is a NOR gate. The output of the NOR gate is clocked to a latch which is preset to the slow condition of the NOR gate. The NOR gate is clocked separately from the clocking of the output of the NOR gate to the latch. A refresh control circuit has an output which is also clocked to the latch. The latch provides an internal address signal for selecting a word line. The internal address signal is representative of the output of the NOR gate when the DRAM is running a data cycle and is representative of the output of the refresh control circuit when the DRAM is running a refresh cycle.

Abstract: An integrated circuit comprises a chip containing electric circuits in a package with leads. The chip receives power via the leads. The leads have inductance so that when there is a change in current flow (di/dt) through a lead there is a voltage which is developed between the end of the lead and the chip which can cause the chip to either malfunction or function poorly. The highest di/dt is generally caused by an output buffer that changes the logic state of its output. The typical output buffer has a pair of driver transistors that provide one of a logic high or logic low. The di/dt generated by these transistors is controlled by controlling the voltage on the gate of the transistor which is providing the particular logic state. This control reduces di/dt from that typically provided at the very beginning of a logic state transition but increases it over that typically provided immediately thereafter for the purpose of optimizing logic state transition speed for a given maximum di/dt.

Abstract: A dynamic random access memory, formed in a substrate, has an array comprised of intersecting rows and columns with memory cells at intersections thereof. Along each row is a plurality of memory cells. Each memory cell has a storage capacitor and a transfer device. The transfer device is a transistor which has gate to which is applied a voltage to select the memory cell. Each transfer device has an insulator between the its gate and the substrate. During a test mode of the memory, all of the transfer gates are subjected to a stress test of this insulator to provide an accelerated test for the integrity of this insulator.

Abstract: A high voltage circuit provides a high voltage signal output in response to receiving a logic signal. The high voltage circuit includes a regenerative circuit which is coupled to a high voltage terminal and a 5 volt power supply terminal. An inverting push-pull buffer responsive to the logic signal provides a signal which is regenerated to the high voltage by the regenerative circuit when the logic signal is in a first state and maintains the signal at ground potential when the logic signal is in a second logic state.