Abstract: The embodiments herein generate parity check data which serves as parity-on-parity. Stated differently, the parity check data can be used to determine if parity data stored in a memory element has been corrupted. For example, after generating the parity data, a computing system may set the parity check data depending on whether there is an even or odd number of logical ones (or logical zeros) in the parity data. Thus, when the parity data is read out of the memory element, if the parity data does not include the same number of even or odd bits, the parity check data indicates to the computing system that the parity data is corrupted. In one embodiment, to reduce the likelihood that the parity check data becomes corrupted, the computing system stores this data in hardened latches which are less susceptible to soft errors than other types of memory elements.

Abstract: Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.

Abstract: Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.

Abstract: A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.

Abstract: A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.

Abstract: A system and method of selective row energization based on write data, with a selective row energization system including a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detect circuit 110 responsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect register 112 having M uniform-detect latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated M row 104; and an M-bit row driver device 116 responsive to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.

Abstract: A system and method of selective row energization based on write data, with a selective row energization system including a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detect circuit 110 responsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect register 112 having M uniform-detect latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated M row 104; and an M-bit row driver device 116 responsive to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.

Abstract: An apparatus for floating read bitlines of a static random access memory (SRAM) is disclosed. The SRAM includes a first and second SRAM cell columns, a first and second read bitlines, and a multiplexor. The multiplexor is coupled to the first and second SRAM cell columns via the first and second read bitlines, respectively. The multiplexor is capable of selectively transmitting data from the first or second SRAM cell column via the first or second read bitline, respectively, to an output. In addition, the multiplexor allows the first read bitline and/or the second read bitline to remain uncharged when no data are being read from the first SRAM cell column and/or the second SRAM cell column.

Abstract: A system and method of selective row energization based on write data, with a selective row energization system including a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detect circuit 110 responsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect register 112 having M uniform-detect latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated M row 104; and an M-bit row driver device 116 responsive to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.