Abstract: A packaged integrated circuit (IC) chip that provides input/output (I/O) signal fail safe verification is disclosed. The packaged IC chip includes a first processing unit, a first control peripheral coupled to receive a first processed signal from the processing unit and to provide an output signal, and compare logic. The compare logic is coupled to receive the output signal and a comparison signal, to compare the output signal and the comparison signal, and to provide an error signal responsive to a difference between the output signal and the comparison signal.

Abstract: In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.

Abstract: A system comprising a processor, a non-transitory memory, and an application stored in the non-transitory memory is provided. The application is configured, upon execution by the processor, to cause the processor to generate a first controller signal based on a first set of feedback from an electric motor, based on a characterization tone, and based on a controller gain, to provide the first controller signal for operation of the electric motor, to generate a frequency response analysis on a second set of feedback from the electric motor in response to the first controller signal, and to determine a new value of the controller gain based on the frequency response analysis.

Abstract: In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.

Abstract: In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.

Abstract: In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.

Abstract: In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.

Abstract: In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.

Abstract: A system comprising a processor, a non-transitory memory, and an application stored in the non-transitory memory is provided. The application is configured, upon execution by the processor, to cause the processor to generate a first controller signal based on a first set of feedback from an electric motor, based on a characterization tone, and based on a controller gain, to provide the first controller signal for operation of the electric motor, to generate a frequency response analysis on a second set of feedback from the electric motor in response to the first controller signal, and to determine a new value of the controller gain based on the frequency response analysis.

Abstract: A packaged integrated circuit (IC) chip that provides input/output (I/O) signal fail safe verification is disclosed. The packaged IC chip includes a first processing unit, a first control peripheral coupled to receive a first processed signal from the processing unit and to provide an output signal, and compare logic. The compare logic is coupled to receive the output signal and a comparison signal, to compare the output signal and the comparison signal, and to provide an error signal responsive to a difference between the output signal and the comparison signal.

Abstract: A system comprising a processor, a non-transitory memory, and an application stored in the non-transitory memory is provided. The application is configured, upon execution by the processor, to cause the processor to generate a first controller signal based on a first set of feedback from an electric motor, based on a characterization tone, and based on a controller gain, to provide the first controller signal for operation of the electric motor, to generate a frequency response analysis on a second set of feedback from the electric motor in response to the first controller signal, and to determine a new value of the controller gain based on the frequency response analysis.

Abstract: A packaged integrated circuit (IC) chip that provides input/output (I/O) signal fail safe verification is disclosed. The packaged IC chip includes a first processing unit, a first control peripheral coupled to receive a first processed signal from the processing unit and to provide an output signal, and compare logic. The compare logic is coupled to receive the output signal and a comparison signal, to compare the output signal and the comparison signal, and to provide an error signal responsive to a difference between the output signal and the comparison signal.

Abstract: A system comprising a processor, a non-transitory memory, and an application stored in the non-transitory memory is provided. The application is configured, upon execution by the processor, to cause the processor to generate a first controller signal based on a first set of feedback from an electric motor, based on a characterization tone, and based on a controller gain, to provide the first controller signal for operation of the electric motor, to generate a frequency response analysis on a second set of feedback from the electric motor in response to the first controller signal, and to determine a new value of the controller gain based on the frequency response analysis.

Abstract: A packaged integrated circuit (IC) chip that provides input/output (I/O) signal fail safe verification is disclosed. The packaged IC chip includes a first processing unit, a first control peripheral coupled to receive a first processed signal from the processing unit and to provide an output signal, and compare logic. The compare logic is coupled to receive the output signal and a comparison signal, to compare the output signal and the comparison signal, and to provide an error signal responsive to a difference between the output signal and the comparison signal.

Abstract: A frequency-controlled power converter includes a power stage frequency response characterization circuit. A PWM input control value F_OL_CTL generates a PWM output control signal to drive the converter to a selected output voltage. F_OL_CTL is added to each of a set of periodic, incrementally time-sequenced discrete frequency deviation control values F_DEV(t) having a periodicity of F_RESP corresponding to a frequency at which a response of the power stage is to be measured. A resulting set of perturbed PWM input control values F_CTL_PTB(t) frequency-modulate the PWM output control signal and perturb the converter output voltage. A corresponding set of perturbed converter output voltage samples V_OUT_PTB(t) is cross-correlated to the set of F_CTL_PTB(t) to generate correlation components of V_OUT_PTB(t) and F_CTL_PTB(t).

Abstract: A frequency-controlled power converter includes a power stage frequency response characterization circuit. A PWM input control value F_OL_CTL generates a PWM output control signal to drive the converter to a selected output voltage. F_OL_CTL is added to each of a set of periodic, incrementally time-sequenced discrete frequency deviation control values F_DEV(t) having a periodicity of F_RESP corresponding to a frequency at which a response of the power stage is to be measured. A resulting set of perturbed PWM input control values F_CTL_PTB(t) frequency-modulate the PWM output control signal and perturb the converter output voltage. A corresponding set of perturbed converter output voltage samples V_OUT_PTB(t) is cross-correlated to the set of F_CTL_PTB(t) to generate correlation components of V_OUT_PTB(t) and F_CTL_PTB(t).

Abstract: A multi-chip module includes a first die having a control processor to generate a signal to control an industrial process and an input/output interface. The multi-chip module also includes a second die having a supervisory processor and an input/output interface. A processor failure of one of the control processor and the supervisory processor is detected by the other of the control processor and the supervisory processor, and the processor that detects the failure is configured to assert a signal through its input/output interface to cause the industrial process to transition to a safe state in response to the failure. Additionally, the first and second dies are created using different process technologies.

Abstract: A multi-chip module includes a first die having a control processor to generate a signal to control an industrial process and an input/output interface. The multi-chip module also includes a second die having a supervisory processor and an input/output interface. A processor failure of one of the control processor and the supervisory processor is detected by the other of the control processor and the supervisory processor, and the processor that detects the failure is configured to assert a signal through its input/output interface to cause the industrial process to transition to a safe state in response to the failure. Additionally, the first and second dies are created using different process technologies.