Abstract: Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.

Abstract: Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.

Abstract: A wideband digital tuner (14′) has an analog front-end section (10), a high speed analog-to-digital converter (12), demultiplexer (13) and a plurality of filters (341-342) arranged in a parallel input architecture to process wideband digital data received at extremely high sampling rates, such as at 2 Gsps (giga-samples per second). The tuner greatly attenuates an undesired spectral half of the wide bandwidth digital spectrum of the incoming digital signal using a complex band-pass filter, such as a Hilbert Transform filter. The tuner places the remaining half of the wide bandwidth digital spectrum of the incoming digital signal at complex baseband and down samples by 2. The architecture of the tuner can be partitioned into two separate halves which are hardware copies of each other.

Abstract: The invention is a demodulator (50, 100) and a method of data reception and testing of a demodulator. A demodulator in accordance with the invention includes an input signal source (52, 102) having an output which during data reception is a data signal and which during testing of the demodulator is a reference signal; a tuner (54, 101) having a tuner input coupled to the output of the input signal source and a tuner output, the tuner including a frequency converter (20, 36) which frequency shifts the data signal to a lower carrier frequency during data reception to cause the tuner to output at the tuner output the lower carrier frequency modulated with the data signal and which upwardly frequency shifts the reference signal to a test carrier frequency during the testing; and a test data source (56, 105) which applies a test data signal to the tuner during the testing to cause the tuner to output at the tuner output the test carrier frequency modulated with the test data signal.