Abstract: A chip-size package includes a semiconductor chip having a plurality of input/output pads on an active surface and a passivation layer covering the active surface such that the pads are exposed. Attached to the chip is a substrate having a plurality of electrically conductive traces and corresponding terminal pads therein. A bottom portion of each of the traces is exposed at the bottom surface of the substrate so that the traces are mechanically and electrically bonded to one of the input/output pads. The terminal pads are formed on a top portion of each of the traces and are exposed to a top surface of the substrate. Accordingly, the terminal pads are not limited to being located over the center or the periphery of the chip where the input/output pads are located, but rather can be arranged over the entire area of the chip to produce a chip-size package capable of mass production.