Abstract: According to exemplary embodiments of the invention, a liquid crystal display is provided which includes a plurality of spacers having different heights or a different distance or different pressure tolerance from a corresponding display panel and disposed in at least two pixel areas displaying different colors. As compared with conventional techniques (e.g., disposing the spacers only in one pixel area), the disposition density of the spacer per pixel area is lowered, such that it is possible to prevent the pressure tolerance of the spacer from intensively acting only on a specific pixel. The pressure tolerance of the spacer is uniformly maintained for every pixel, so that insufficiency of the amount of dropping liquid crystal is avoided. As a result, it is possible to prevent the light leakage caused by the insufficient liquid crystal.

Abstract: The display panel includes an opposite substrate and an array substrate. The opposite substrate includes a first substrate including a first surface and a second surface opposite to the first surface, a first wire electrode formed on the first surface, a first transparent electrode formed on the first surface and partially overlapping with the first wire electrode, and a common electrode formed on the second surface. The first wire on the first surface is formed before the first transparent electrode on the first surface. The array substrate includes a second substrate including a third surface facing the second surface, and a pixel layer formed on the third surface and facing the common electrode.

Abstract: According to exemplary embodiments of the invention, a liquid crystal display is provided which includes a plurality of spacers having different heights or a different distance or different pressure tolerance from a corresponding display panel and disposed in at least two pixel areas displaying different colors. As compared with conventional techniques (e.g., disposing the spacers only in one pixel area), the disposition density of the spacer per pixel area is lowered, such that it is possible to prevent the pressure tolerance of the spacer from intensively acting only on a specific pixel. The pressure tolerance of the spacer is uniformly maintained for every pixel, so that insufficiency of the amount of dropping liquid crystal is avoided. As a result, it is possible to prevent the light leakage caused by the insufficient liquid crystal.

Abstract: The display panel includes an opposite substrate and an array substrate. The opposite substrate includes a first substrate including a first surface and a second surface opposite to the first surface, a first wire electrode formed on the first surface, a first transparent electrode formed on the first surface and partially overlapping with the first wire electrode, and a common electrode formed on the second surface. The first wire on the first surface is formed before the first transparent electrode on the first surface. The array substrate includes a second substrate including a third surface facing the second surface, and a pixel layer formed on the third surface and facing the common electrode.

Abstract: A semiconductor chip testing system comprises a tester with a predetermined number of pin drivers; high current and low current drivers are connected between the pin drivers of the tester and a ground voltage applying terminal of the semiconductor chip to be tested. Control signals are applied to the pin drivers according to a testing method of a tester to generate ground noise at the ground voltage applying terminal of the semiconductor chip, thereby performing a ground noise immunity test on the semiconductor chip. A semiconductor chip tester comprises a predetermined number of pin drivers with large current driving capacity; and a predetermined number of pin drivers with small current driving capacity, wherein ground noise control signals are applied to the pin drivers with large current driving capacity according to a test program to apply ground noise to a ground voltage applying terminal of a semiconductor chip to be tested while the semiconductor chip is tested according to the test program.