Patents by Inventor Sam-Jong Choi
Sam-Jong Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230201992Abstract: A method of polishing a substrate having amorphous carbon layer deposited thereon removes protrusions on the ACL surface by using a soft pad with a low hardness and a polishing slurry containing non-spherical modified fumed silica with high friction force with the surface.Type: ApplicationFiled: December 22, 2022Publication date: June 29, 2023Inventors: Heesuk KIM, Goo Hwa LEE, Jaehong YOO, Jong Dai PARK, Jae Hyun KIM, Juyoung YUN, Jisung LEE, Seonung CHOI, Jae-hwi LEE, Bong Soo AHN, Sam-jong CHOI
-
Publication number: 20230008927Abstract: A system and a method for reusing carbon dioxide are provided. The system includes: a process apparatus configured to discharge exhaust gas containing carbon dioxide therefrom; a purifying device configured to purify the exhaust gas, and thus produce reused carbon dioxide from the exhaust gas and store the produced reused carbon dioxide; a first supply tank configured to receive the reused carbon dioxide from the purifying device; a second supply tank configured to receive the reused carbon dioxide from the first supply tank and provide the reused carbon dioxide to the process apparatus; and a blocking device configured to, based on determining that a purity of the reused carbon dioxide provided from the purifying device to the first supply tank fails to satisfy a predefined reference, block flow of the reused carbon dioxide from the purifying device to the first supply tank.Type: ApplicationFiled: December 6, 2021Publication date: January 12, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin Soo KIM, Myung Beom PARK, Dong-Min KANG, Sam Jong CHOI
-
Patent number: 9806036Abstract: A semiconductor wafer including a main body including first and second surfaces opposite each other, a notch including a recess on an outer periphery, a first bevel region formed along the outer periphery of the main body, including a first slope connecting the first and second surfaces and having a first height with respect to a straight line extending from a first point where the first surface and the first slope meet to a second point where the second surface and the first slope meet, and a second bevel region in contact with the recess or opening, including a second slope connecting the first and second surfaces and having a second height, different from the first height, with respect to a straight line extending from a third point where the first surface and the second slope meet to a fourth point where the second surface and the second slope meet.Type: GrantFiled: November 17, 2016Date of Patent: October 31, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-soo Kim, Sam-jong Choi, Sue-ryeon Kim, Tae-hyoung Koo, Hyun-hee Ju, Cheong-jun Kim, Ji-won You
-
Publication number: 20170200683Abstract: A semiconductor wafer including a main body including first and second surfaces opposite each other, a notch including a recess on an outer periphery, a first bevel region formed along the outer periphery of the main body, including a first slope connecting the first and second surfaces and having a first height with respect to a straight line extending from a first point where the first surface and the first slope meet to a second point where the second surface and the first slope meet, and a second bevel region in contact with the recess or opening, including a second slope connecting the first and second surfaces and having a second height, different from the first height, with respect to a straight line extending from a third point where the first surface and the second slope meet to a fourth point where the second surface and the second slope meet.Type: ApplicationFiled: November 17, 2016Publication date: July 13, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: JONG-SOO KIM, Sam-jong Choi, Sue-ryeon Kim, Tae-hyoung Koo, Hyun-hee Ju, Cheong-jun Kim, Ji-won You
-
Publication number: 20150340445Abstract: A substrate structure include a lower substrate doped with n-type impurities having a first impurity concentration, an epitaxial layer on the lower substrate, and a metallic-contaminant collection area spaced apart from the epitaxial layer in the lower substrate, the metallic-contaminant collection area doped with impurities having a second impurity concentration higher than the first impurity concentration, the metallic-contaminant collection area having lattice defects, and an upper surface of the metallic-contaminant collection area being spaced apart from a top surface of the lower substrate at a distance in a range of about 0.1 ?m to about 3 ?m.Type: ApplicationFiled: March 12, 2015Publication date: November 26, 2015Inventors: Joon-Young CHOI, Tae-Gon KIM, Hyun-Pil NOH, Jae-Sik BAE, Sam-Jong CHOI
-
Patent number: 9190464Abstract: A nonvolatile memory device includes a substrate, an elongate isolation region including a field insulation film disposed in a trench in the substrate, and a word line crossing the insulation region and including a tunneling insulation layer on an active region of the substrate adjacent the isolation region, a charge storage layer on the tunneling insulation layer and a blocking insulation layer on the charge storage layer. A first plane index of a bottom surface of the trench has a first interface trap density and a second plane index of a sidewall of the trench has a second interface trap density equal to or less than the first interface trap density. In some embodiments, the first plane index may be (100) and the second plane index may be (100) or (310).Type: GrantFiled: December 20, 2013Date of Patent: November 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Joon-Young Choi, Sang-Eun Lee, Sam-Jong Choi, Jin-Ho Kim
-
Patent number: 9035309Abstract: A three-dimensional (3D) CMOS image sensor (CIS) that sufficiently absorbs incident infrared-rays (IRs) and includes an infrared-ray (IR) receiving unit formed in a thin epitaxial film, thereby being easily manufactured using a conventional CIS process, a sensor system including the 3D CIS, and a method of manufacturing the 3D CIS, the 3D CIS including an IR receiving part absorbing IRs incident thereto by repetitive reflection to produce electron-hole pairs (EHPs); and an electrode part formed on the IR receiving part and collecting electrons produced by applying a predetermined voltage thereto.Type: GrantFiled: January 5, 2011Date of Patent: May 19, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Young-soo Park, Won-joo Kim, Kyoo-chul Cho, Gi-jung Kim, Sam-jong Choi
-
Publication number: 20140197465Abstract: A nonvolatile memory device includes a substrate, an elongate isolation region including a field insulation film disposed in a trench in the substrate, and a word line crossing the insulation region and including a tunneling insulation layer on an active region of the substrate adjacent the isolation region, a charge storage layer on the tunneling insulation layer and a blocking insulation layer on the charge storage layer. A first plane index of a bottom surface of the trench has a first interface trap density and a second plane index of a sidewall of the trench has a second interface trap density equal to or less than the first interface trap density. In some embodiments, the first plane index may be (100) and the second plane index may be (100) or (310).Type: ApplicationFiled: December 20, 2013Publication date: July 17, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Joon-Young Choi, Sang-Eun Lee, Sam-Jong Choi, Jin-Ho Kim
-
Publication number: 20140008705Abstract: A semiconductor device includes field regions formed in a substrate, and n-type impurity regions disposed between the field regions. At least one of the side surfaces of the field regions has a {100}, {310}, or {311} plane.Type: ApplicationFiled: March 15, 2013Publication date: January 9, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joon- Young Choi, Kyung-Ho Lee, Sang-Jun Choi, Tae-Hyoung Koo, Sam-Jong Choi
-
Patent number: 8497570Abstract: A wafer, a fabricating method of the same, and a semiconductor substrate are provided. The wafer includes a first substrate layer formed at a first surface, a second substrate layer formed at a second surface opposite to the first surface, the second substrate layer having a greater oxygen concentration than the first substrate layer, and an oxygen diffusion protecting layer formed between the first substrate layer and the second substrate layer, the oxygen diffusion protecting layer being located closer to the first surface than to the second surface.Type: GrantFiled: July 8, 2011Date of Patent: July 30, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Ha Hwang, Young-Soo Park, Sam-Jong Choi, Joon-Young Choi, Tae-Hyoung Koo
-
Patent number: 8343853Abstract: A method of processing a semiconductor wafer includes preheating the wafer to a preheating temperature that is less than a peak temperature, heating the wafer from the preheating temperature to the peak temperature at a first ramp rate that averages about 100° C. per second or more, and, immediately after heating the wafer from the preheating temperature to the peak temperature, cooling the wafer at a second ramp rate that averages about ?70° C. per second or more from the peak temperature to the preheating temperature, wherein the peak temperature is about 1,100° C. or more.Type: GrantFiled: October 1, 2009Date of Patent: January 1, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Hyoung Koo, Sam-jong Choi, Yeonsook Kim, Taesung Kim, Heesung Kim, KyooChul Cho, Joonyoung Choi
-
Publication number: 20120056304Abstract: A wafer, a fabricating method of the same, and a semiconductor substrate are provided. The wafer includes a first substrate layer formed at a first surface, a second substrate layer formed at a second surface opposite to the first surface, the second substrate layer having a greater oxygen concentration than the first substrate layer, and an oxygen diffusion protecting layer formed between the first substrate layer and the second substrate layer, the oxygen diffusion protecting layer being located closer to the first surface than to the second surface.Type: ApplicationFiled: July 8, 2011Publication date: March 8, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun-Ha Hwang, Young-Soo Park, Sam-Jong Choi, Joon-Young Choi, Tae-Hyoung Koo
-
Publication number: 20110193940Abstract: A three-dimensional (3D) CMOS image sensor (CIS) that sufficiently absorbs incident infrared-rays (IRs) and includes an infrared-ray (IR) receiving unit formed in a thin epitaxial film, thereby being easily manufactured using a conventional CIS process, a sensor system including the 3D CIS, and a method of manufacturing the 3D CIS, the 3D CIS including an IR receiving part absorbing IRs incident thereto by repetitive reflection to produce electron-hole pairs (EHPs); and an electrode part formed on the IR receiving part and collecting electrons produced by applying a predetermined voltage thereto.Type: ApplicationFiled: January 5, 2011Publication date: August 11, 2011Inventors: Young-soo Park, Won-joo Kim, Kyoo-chul Cho, Gi-jung Kim, Sam-jong Choi
-
Patent number: 7964907Abstract: Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.Type: GrantFiled: May 19, 2009Date of Patent: June 21, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sam-jong Choi, Yong-kwon Kim, Kyoo-chul Cho, Kyung-soo Kim, Jae-ryong Jung, Tae-soo Kang, Sang-Sig Kim
-
Publication number: 20100148310Abstract: A method of processing a semiconductor wafer includes preheating the wafer to a preheating temperature that is less than a peak temperature, heating the wafer from the preheating temperature to the peak temperature at a first ramp rate that averages about 100° C. per second or more, and, immediately after heating the wafer from the preheating temperature to the peak temperature, cooling the wafer at a second ramp rate that averages about ?70° C. per second or more from the peak temperature to the preheating temperature, wherein the peak temperature is about 1,100° C. or more.Type: ApplicationFiled: October 1, 2009Publication date: June 17, 2010Inventors: Tae-Hyoung Koo, Sam-jong Choi, Yeonsook Kim, Taesung Kim, Heesung Kim, KyooChul Cho, Joonyoung Choi
-
Publication number: 20090236655Abstract: Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.Type: ApplicationFiled: May 19, 2009Publication date: September 24, 2009Inventors: Sam-jong Choi, Yong-kwon Kim, Kyoo-chul Cho, Kyung-soo Kim, Jae-ryong Jung, Tae-soo Kang, Sang-Sig Kim
-
Patent number: 7573123Abstract: Provided are a semiconductor device, and a method of forming the same. In one embodiment, the semiconductor device includes a semiconductor layer, first and second semiconductor fins, an insulating layer, and an inter-fin connection member. The first and second semiconductor fins are placed on the semiconductor layer, and have different crystal directions. The first semiconductor fin is connected to the semiconductor layer, and has the equivalent crystal direction as that of the semiconductor layer. The insulating layer is interposed between the second semiconductor fin and the semiconductor layer, and has an opening in which the first semiconductor fin is inserted. The inter-fin connection member connects the first semiconductor fin and the second semiconductor fin together on the insulating layer.Type: GrantFiled: July 9, 2007Date of Patent: August 11, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Soo Park, Kyoo-Chul Cho, Hee-Sung Kim, Tae-Soo Kang, Sam-Jong Choi
-
Patent number: 7550347Abstract: Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.Type: GrantFiled: August 25, 2006Date of Patent: June 23, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sam-jong Choi, Yong-kwon Kim, Kyoo-chul Cho, Kyung-soo Kim, Jae-ryong Jung, Tae-soo Kang, Sang-Sig Kim
-
Publication number: 20090096014Abstract: A nonvolatile memory device includes a semiconductor substrate, a charge-trap structure disposed on the semiconductor substrate, which includes an insulating film and a plurality of carbon nanocrystals embedded in the insulating film, and a gate disposed on the charge-trap structure. The nonvolatile memory device may exhibit memory hysteresis characteristics with improved reliability.Type: ApplicationFiled: June 11, 2008Publication date: April 16, 2009Inventors: Sam-Jong Choi, Kyoo-Chul Cho, Jung-Sik Choi, Hee-sung Kim, Tae-Soo Kang, Yoon-Hee Lee
-
Publication number: 20080246077Abstract: In a method for fabricating a semiconductor memory device and a semiconductor memory device fabricated by the method, the method includes forming a multi-layered dielectric structure including a first dielectric layer with an ion implantation layer and a second dielectric layer without an ion implantation layer, over a semiconductor substrate; forming nanocrystals in the first and second dielectric layers by diffusing ions of the ion implantation layer by thermally treating the multi-layered dielectric structure; and forming a gate electrode on the multi-layered dielectric structure.Type: ApplicationFiled: February 4, 2008Publication date: October 9, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Soo Park, Sam-Jong Choi, Kyoo-Chul Cho, Tae-Soo Kang