Abstract: A client-server system that performs machine learning based information fusion to predict part failure likelihood is described. The system receives transactional data pertaining to replacement of, and sensor data pertaining to duty cycle of, one or more parts. The system trains a first machine learning model, using the transactional data as training data, to extract a plurality of concepts corresponding to the information present in unstructured text in the transactional data. The system also trains a second machine learning model, using the sensor data and the extracted plurality of concepts, to predict part failure likelihood of the one or more parts. The system determines the part failure likelihood of the one or more parts by providing new transactional data and new sensor data to the trained machine learning models.

Abstract: A client-server system that performs machine learning based information fusion to predict part failure likelihood is described. The system receives transactional data pertaining to replacement of, and sensor data pertaining to duty cycle of, one or more parts. The system trains a first machine learning model, using the transactional data as training data, to extract a plurality of concepts corresponding to the information present in unstructured text in the transactional data. The system also trains a second machine learning model, using the sensor data and the extracted plurality of concepts, to predict part failure likelihood of the one or more parts. The system determines the part failure likelihood of the one or more parts by providing new transactional data and new sensor data to the trained machine learning models.

Abstract: An in vitro tissue plate may include a well plate, a fluidic plate disposed on a bottom surface of the well plate, and a media manifold disposed on a bottom surface of the fluidic plate. The well plate may have at least two wells, including a tissue well and a waste well. The fluid plate may include a fluid channel extending between and fluidly connecting the tissue well to the waste well. The media manifold may include a one or more media outlets fluidly connected to the fluid channel. A tissue layer may be deposited in the tissue well. The tissue layer may include human cells such as neurovascular cells.

Abstract: A client-server system that performs machine learning based information fusion to predict part failure likelihood is described. The system receives transactional data pertaining to replacement of, and sensor data pertaining to duty cycle of, one or more parts. The system trains a first machine learning model, using the transactional data as training data, to extract a plurality of concepts corresponding to the information present in unstructured text in the transactional data. The system also trains a second machine learning model, using the sensor data and the extracted plurality of concepts, to predict part failure likelihood of the one or more parts. The system determines the part failure likelihood of the one or more parts by providing new transactional data and new sensor data to the trained machine learning models.

Abstract: A scalable automated maintenance optimisation system for managing replacement of parts in a portfolio of assets is described. A plurality of maintenance records pertaining to one or more replaced parts is received. The received plurality of maintenance records is analysed to generate an asset history including information on replacement of parts. An age at replacement distribution is generated for each part type based on the asset history. A part replacement strategy for each part type is determined based at least on the calculated age at replacement distribution. A user interface is controlled to display a list of the parts and the respective determined part replacement strategy. The displayed list automatically reconfigured by moving parts whose determined part replacement strategy is different from a current part replacement strategy to a position closer to the top of the displayed list of parts in the user interface.

Abstract: During software development for embedded systems, it is very common to use a remote debugger to debug the software applications. In such a debugging environment, the debugger will be running on a remote computer and the application under development will be running on the embedded system. The debugger will be connected to the embedded system via a software link or a hardware emulator. During the debug process, it is desirable to access various memory blocks in the embedded system in different ways. An example would be to enable or disable CPU cache during memory access for a specific address range. Another example would be the ability to designate a memory block as a flash memory to allow the use of a programming algorithm. This feature is addressed by adding a Memory Access Table (MAT) from a configuration file or compiler output to the debugger, emulator or debug monitor.

Abstract: A software compiler is described here that is capable of analyzing JTAG test functions and translating them into code and date usable and accessible by a JTAG-bus controller hardware circuit. The compiler is capable of reading instructions and data information not directly usable by a JTAG-bus controller, such as Serial Victor Format, and generating instructions and data executable by a JTAG-bus controller hardware circuit. This allows the JTAG-bus controller to directly access such compiled code during the test without using an interpreter to translate such information before executing them. The Compiler is also capable of allocating and managing a memory structure to store multiple data structure at the same time so that it will be ready to be used by the JTAG-bus controller during scan operations. This will allow for an expedited execution of the test functions since the data is already translated into directly readable and writable formats.

Abstract: During software development for embedded systems, it is very common to use a remote debugger to debug the software applications. In such a debugging environment, the debugger will be running on a remote computer and the application under development will be running on the embedded system. The debugger will be connected to the embedded system via a software link or a hardware emulator. During the debug process, it is desirable to access various memory blocks in the embedded system in different ways. An example would be to enable or disable CPU cache during memory access for a specific address range. Another example would be the ability to designate a memory block as a flash memory to allow the use of a programming algorithm. This feature is addressed by adding a Memory Access Table (MAT) from a configuration file or compiler output to the debugger, emulator or debug monitor.

Abstract: A test and debug processor capable of initiating, commanding and executing JTAG-bus functions without the involvement of an external CPU. The processor includes a JTAG-bus controller with a JTAG port coupled to it. The JTAG-bus functions are encoded in instructions and stored in a memory structure. The processor instructions are then fetched and executed directly by the JTAG-bus controller without software interpretation. The instructions optionally includes JTAG-bus end state, function duration information, information about the location of the data to be sent out to the test object and a location to store the information received from the test object. Optionally, the test and debug processor can directly access any memory structure to fetch or store test data objects by adding a memory bus-controller interface to the processor. The ability to execute arithmetic and logic operation and register transfer operations on test data can be added using an ALU.

Abstract: A Test and debug processor that can execute JTAG scans without the involvement of an external CPU or dedicated hardware. The processor includes a JTAG-bus controller logic, a JTAG port coupled to the JTAG-bus controller logic, memory capable of storing JTAG instructions, and an instruction decoding unit capable of fetching or requesting JTAG instructions from the memory. During use, the JTAG scan functions are encoded in instructions that are natively executable by the processor hardware without software interpretation. The instructions are then stored in a memory structure, fetched and executed directly by the processor. The instruction could optionally include the end-state of the bus after the operation, information about the bit count of the data to be scanned, information about the location of the data to be sent out of the JTAG port and also the location to store the received information from the test subject.