Patents by Inventor Sam Povilus

Sam Povilus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12693845
    Abstract: This application is directed to managing firmware control data stored in a memory device of an electronic device. The electronic device obtains a current data descriptor map (DDM) corresponding to a current version of a firmware program, and identifies, in the memory device, a prior DDM and a prior control data structure corresponding to a prior version of the firmware program. Each of the prior and current DDMs maps a plurality of data descriptors to a plurality of locations in a respective control data structure. The prior control data structure stores a plurality of prior control data items identified by a plurality of prior data descriptors. A current control data structure is automatically generated for the current version of the firmware program based on the prior control data structure, the current DDM, and the prior DDM, and stores a plurality of current control data items identified by the data descriptors.
    Type: Grant
    Filed: November 10, 2023
    Date of Patent: July 28, 2026
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Sam Povilus, Cody Dinges, Karl Heichelheim
  • Publication number: 20260203045
    Abstract: A system and related method, including a first processor core, a second processor core and a control circuitry to receive requests to update existing firmware of the first processor core to a new firmware. The control circuitry loads existing firmware onto the second processor core and migrates data associated with the existing firmware on the first processor core to the second processor core. The control circuitry stops the transaction execution by the first processor core while causing the second processor core to execute transactions in place of the first processor core. The control circuitry restarts the first processor core, replaces the existing firmware on the first processor core with the new firmware, and migrates data of the existing firmware on the second processor core to the first processor core. The control circuitry stops the transaction execution of the second processor core and causes the first processor core to execute transactions.
    Type: Application
    Filed: March 13, 2026
    Publication date: July 16, 2026
    Inventors: Timothy Hallett, Bindu Madhavi Khambam, Kailaash Rajagopalan, Mahesh Govindane, Matthew Fitzpatrick, Sam Povilus, John Nolan, Jonathan M. Hughes
  • Patent number: 12596546
    Abstract: A system and related method, including a first processor core, a second processor core and a control circuitry to receive requests to update existing firmware of the first processor core to a new firmware. The control circuitry loads existing firmware onto the second processor core and migrates data associated with the existing firmware on the first processor core to the second processor core. The control circuitry stops the transaction execution by the first processor core while causing the second processor core to execute transactions in place of the first processor core. The control circuitry restarts the first processor core, replaces the existing firmware on the first processor core with the new firmware, and migrates data of the existing firmware on the second processor core to the first processor core. The control circuitry stops the transaction execution of the second processor core and causes the first processor core to execute transactions.
    Type: Grant
    Filed: May 24, 2024
    Date of Patent: April 7, 2026
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Timothy Hallett, Bindu Madhavi Khambam, Kailaash Rajagopalan, Mahesh Govindane, Matthew Fitzpatrick, Sam Povilus, John Nolan, Jonathan M. Hughes
  • Patent number: 12561076
    Abstract: A method for updating a device includes receiving an instruction to update from a first configuration in the device to a second configuration, where a first heap memory allocated to the first configuration includes multiple first allocated memory blocks and corresponding first memory blocks metadata. The method also includes performing a warm reset, the reset including determining, based on the first memory blocks metadata, that when updating from the first configuration to the second configuration, data of at least one of the first allocated memory blocks should be persisted to a second heap memory allocated to the second configuration, and causing the device to update from the first configuration to the second configuration, where the update includes persisting, based on the first memory blocks metadata, the data of at least one of the first allocated memory blocks to a second heap memory allocated to the second configuration.
    Type: Grant
    Filed: June 18, 2024
    Date of Patent: February 24, 2026
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Matthew Fitzpatrick, Craig Valine, Kailaash Rajagopalan, Mahesh Govindane, Sam Povilus
  • Publication number: 20250383798
    Abstract: A method for updating a device includes receiving an instruction to update from a first configuration in the device to a second configuration, where a first heap memory allocated to the first configuration includes multiple first allocated memory blocks and corresponding first memory blocks metadata. The method also includes performing a warm reset, the reset including determining, based on the first memory blocks metadata, that when updating from the first configuration to the second configuration, data of at least one of the first allocated memory blocks should be persisted to a second heap memory allocated to the second configuration, and causing the device to update from the first configuration to the second configuration, where the update includes persisting, based on the first memory blocks metadata, the data of at least one of the first allocated memory blocks to a second heap memory allocated to the second configuration.
    Type: Application
    Filed: June 18, 2024
    Publication date: December 18, 2025
    Inventors: Matthew Fitzpatrick, Craig Valine, Kailaash Rajagopalan, Mahesh Govindane, Sam Povilus
  • Publication number: 20250156170
    Abstract: This application is directed to managing firmware control data stored in a memory device of an electronic device. The electronic device obtains a current data descriptor map (DDM) corresponding to a current version of a firmware program, and identifies, in the memory device, a prior DDM and a prior control data structure corresponding to a prior version of the firmware program. Each of the prior and current DDMs maps a plurality of data descriptors to a plurality of locations in a respective control data structure. The prior control data structure stores a plurality of prior control data items identified by a plurality of prior data descriptors. A current control data structure is automatically generated for the current version of the firmware program based on the prior control data structure, the current DDM, and the prior DDM, and stores a plurality of current control data items identified by the data descriptors.
    Type: Application
    Filed: November 10, 2023
    Publication date: May 15, 2025
    Inventors: Sam POVILUS, Cody DINGES, Karl HEICHELHEIM
  • Publication number: 20240311141
    Abstract: A system and related method, including a first processor core, a second processor core and a control circuitry to receive requests to update existing firmware of the first processor core to a new firmware. The control circuitry loads existing firmware onto the second processor core and migrates data associated with the existing firmware on the first processor core to the second processor core. The control circuitry stops the transaction execution by the first processor core while causing the second processor core to execute transactions in place of the first processor core. The control circuitry restarts the first processor core, replaces the existing firmware on the first processor core with the new firmware, and migrates data of the existing firmware on the second processor core to the first processor core. The control circuitry stops the transaction execution of the second processor core and causes the first processor core to execute transactions.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Inventors: Timothy Hallett, Bindu Madhavi Khambam, Kailaash Rajagopalan, Mahesh Govindane, Matthew Fitzpatrick, Sam Povilus, John Nolan, Jonathan M. Hughes
  • Patent number: 12026506
    Abstract: A system and related method, including a first processor core, a second processor core and a control circuitry to receive requests to update existing firmware of the first processor core to a new firmware. The control circuitry loads existing firmware onto the second processor core and migrates data associated with the existing firmware on the first processor core to the second processor core. The control circuitry stops the transaction execution by the first processor core while causing the second processor core to execute transactions in place of the first processor core. The control circuitry restarts the first processor core, replaces the existing firmware on the first processor core with the new firmware, and migrates data of the existing firmware on the second processor core to the first processor core. The control circuitry stops the transaction execution of the second processor core and causes the first processor core to execute transactions.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: July 2, 2024
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Timothy Hallett, Bindu Madhavi Khambam, Kailaash Rajagopalan, Mahesh Govindane, Matthew Fitzpatrick, Sam Povilus, John Nolan, Jonathan M. Hughes
  • Publication number: 20240012635
    Abstract: A system and related method, including a first processor core, a second processor core and a control circuitry to receive requests to update existing firmware of the first processor core to a new firmware. The control circuitry loads existing firmware onto the second processor core and migrates data associated with the existing firmware on the first processor core to the second processor core. The control circuitry stops the transaction execution by the first processor core while causing the second processor core to execute transactions in place of the first processor core. The control circuitry restarts the first processor core, replaces the existing firmware on the first processor core with the new firmware, and migrates data of the existing firmware on the second processor core to the first processor core. The control circuitry stops the transaction execution of the second processor core and causes the first processor core to execute transactions.
    Type: Application
    Filed: July 8, 2022
    Publication date: January 11, 2024
    Inventors: Timothy Hallett, Bindu Madhavi Khambam, Kailaash Rajagopalan, Mahesh Govindane, Matthew Fitzpatrick, Sam Povilus, John Nolan, Jonathan M. Hughes