Abstract: A CMOS low noise band gap reference circuit outputs a substantially constant reference voltage VREF. The band gap reference circuit has an amplifier that includes a differential pair of bipolar junction transistors and a feedback circuit that adjusts its current to compensate for variations in the bias current through the circuit. The band gap reference circuit provides an output reference voltage VREF that is substantially constant over a range of temperature and a range of supply voltage.

Abstract: The present invention comprises an input amplifier circuit that provides a low input offset voltage amplified output signal. Input amplifiers of the present invention include a differential pair of transistors that may be fabricated using standard CMOS process steps. Each transistor in the differential pair includes a parasitic transistor that reduces the current through the associated differential pair transistor. The differential pair has a single ended output coupled to the input of a second amplifier such as a MOSFET. The current through the second amplifier determines the output signal VOUT. The second amplifier is coupled to a third transistor which also includes a parasitic transistor. The third transistor provides a bias current to the second amplifier that is proportional to the current through the differential pair transistors.

Abstract: The present invention provides a CMOS low noise band gap reference circuit that outputs a substantially constant reference voltage VREF. Band gap reference circuits of the present invention have an amplifier that includes a differential pair of bipolar junction transistors and a feedback circuit that adjusts it current to compensate for variations in the bias current through the circuit. The band gap reference circuits of the present invention provide a output reference voltage VREF that is substantially constant over a range of temperature and a range of supply voltage.

Abstract: The present invention comprises an input amplifier circuit that provides a low input offset voltage amplified output signal. Input amplifiers of the present invention include a differential pair of transistors that may be fabricated using standard CMOS process steps. Each transistor in the differential pair includes a parasitic transistor that reduces the current through the associated differential pair transistor. The differential pair has a single ended output coupled to the input of a second amplifier such as a MOSFET. The current through the second amplifier determines the output signal VOUT. The second amplifier is coupled to a third transistor which also includes a parasitic transistor. The third transistor provides a bias current to the second amplifier that is proportional to the current through the differential pair transistors.

Abstract: A power module having at least one power transistor. Each power transistor is coupled to and protected by an overvoltage clamp and desaturation detection circuit. An output current measurement system is coupled to the power module output. A junction temperature sensor is coupled to each power transistor. An isolation transformer is associated with each power transistor, the primary windings of which are connected to an isolated driver communications interface which converts logic signals to primary winding drive signals. An isolated gate driver is coupled to the secondary winding of each isolation transformer and the gate terminal of each power transistor.

Abstract: An apparatus for suppressing voltage transients and detecting desaturation conditions in power transistor systems. A first transistor, usually a power transistor, has a first terminal, a second terminal, a drive terminal, and an avalanche breakdown voltage rating between the first mad second terminals. The cathode of a first diode is coupled to the first terminal of the first transistor. The first diode has a reverse breakdown voltage which is less than the avalanche breakdown voltage rating of the first transistor. The anode of a second diode is coupled to the anode of the first diode, and the cathode of the second diode is coupled to the drive terminal of the first transistor. Driver circuitry is also coupled to the drive terminal, and provides a drive signal to the first transistor. An RC network comprising a first resistor and a first capacitor is coupled to the driver circuitry. The base terminal of a second transistor is coupled to the driver circuitry by means of the RC network.

Abstract: A high speed, low power, latching, difference amplifier giving Feedback Emitter Coupled Logic level output voltages. The comparator operates with low voltage swings between logic levels to minimize propagation delay and heat dissipation. Efficiency is aided by diverting unneeded current away from the input stage to the latch stage during the latch enabled state, and the input slew rate to the comparator is effectively increased by clamping the input terminals with Schottky diodes. The amplifier works on a restricted common mode range, and normally has its reference voltage input grounded, although other reference voltages may be used. The output can be either positive or negative true. Propagation delay is under 4 nanoseconds, minimum sensitivity is 5 millivolts, and heat dissipation is under 50 milliwatts.

Abstract: JFET and bipolar transistor devices are combined into an analog signal switching circuit. A JFET acts as a switch device for controlling analog signals. The JFET gate is charged through a bipolar transistor to turn if off and discharged through a second bipolar transistor to turn it on. A second JFET is used to control the conduction of the second bipolar transistor so that it only conducts heavily when a high slew rate is needed. The circuit can switch analog signals very rapidly and yet has very low quiescent current drain in both off and on states. The circuit is very simple and is amenable to monolithic integrated circuit construction.

Abstract: A base junction transistor inverter circuit will be driven into the saturation region if the drive current is large enough. In such circumstances, the collector voltage can go below the base voltage and approaches the emitter voltage. A circuit is provided to keep the transistor out of saturation and is comprised of a p-channel field effect transistor (JFET) connected between the base and collector of the junction transistor. The JFET is connected such that when the drive current increases and the junction transistor approaches saturation, the drive current is diverted through the JFET and into the substrate. The same clamp can be implemented by using a pnp junction transistor in combination with an n-channel JFET.

Abstract: A JFET is coupled in parallel with a bipolar transistor to produce a composite structure that has improved signal transfer characteristics in certain circuit applications. While useful with discrete devices, the combination is readily achieved in integrated circuit form.

Abstract: JFET and bipolar transistor devices are combined into an analog signal switching circuit. A JFET acts as a switch device for controlling analog signals. The JFET gate is charged through a bipolar transistor to turn it off and discharged through a second bipolar transistor to turn it on. A second JFET is used to control the conduction of the second bipolar transistor so that it only conducts heavily when a high slew rate is needed. The circuit can switch analog signals very rapidly and yet has very low quiescent current drain in both off and on states. The circuit is very simple and is amenable to monolithic integrated circuit construction.

Abstract: A pair of FET's are coupled in series between the emitter and collector of a bipolar transistor and the juncture of the FET's coupled to the bipolar transistor base. The FET gates are coupled to the bipolar transistor collector. When a current is passed through the emitter-collector terminals in excess of a threshold value, a constant voltage will appear over a substantial current range. The constant voltage is related to FET Vp and can be used to compensate or track integrated circuits that contain both FET's and bipolar transistors.

Abstract: A field effect transistor (FET) is designed to act as an off-on type switch by the control of a driver voltage applied to its gate electrode. A driver circuit, responsive to a toggling current, provides a control of gate electrode voltage. The circuit includes means for rapidly switching the FET on and off while drawing relatively low current in the off and on states. Improvements relate to means for speeding up turn on time and reducing charge transferred to the circuit being switched by the FET.

Abstract: A differential input is applied to four bridge-connected field effect transistors. The bridge drives a differential common base transistor stage. The output can be either differential or single ended as desired taken from the transistor collectors. The circuit provides good common mode rejection and good differential response to signals over a common mode range that exceeds the voltage of the power supply.

Abstract: A circuit for cancelling the offset voltage of a signal amplifier includes a second amplifier and a third amplifier connected to the outputs of the signal amplifier and the second amplifier. A capacitor is connected between the inputs of the second amplifier for storing the offset voltages of the amplifiers thereon. A switch connects the output of the third amplifier to the capacitor and a switch connects the inputs of the signal amplifier together during offset correction. When the offset voltages are stored on the capacitor, the switches open to permit signal amplification and cancellation of the offset voltages. In a second embodiment, a second capacitor stores the instantaneous amplitude of the signal being amplified and supplies it to an input of the second amplifier such that a discontinuity will not appear in the circuit output during offset correction.