Patents by Inventor Sam Zhao

Sam Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250140693
    Abstract: Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including a backside power distribution network. In various embodiments, an apparatus includes a first substrate comprising a device configured to receive a voltage and a first side located on a front side of the first substrate and a second side located on a back side of the first substrate, a second substrate, the second substrate configured to support the first substrate, and a power distribution network located at an interface between the second side of the first substrate and the second substrate.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 1, 2025
    Inventors: Sam Zhao, Xiaoming Li, Qing Liu
  • Patent number: 12277451
    Abstract: A method of provisioning virtual machines (VMs) includes: providing a VM pool that includes a graphics processing unit (GPU)-optimized VM and a non-GPU-optimized VM operating in different clouds. A control plane can receive an indication that a user has submitted a workload request, determine whether a GPU-optimized VM is available and instruct the non-GPU-optimized VM to send the workload to the GPU-optimized VM in a peer-to-peer manner. The GPU-optimized VM computes the workload and returns a result to the requesting VM. The control plane can instantiate a new GPU-optimized VM (or terminate it when the workload is complete) to dynamically maintain a desired number of available GPU-optimized VMs.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: April 15, 2025
    Assignee: Omnissa, LLC
    Inventors: Sam Zhao, Bomin Nie, Nan Wang, Jingtao Zhang, Zhifu Jin
  • Publication number: 20250096108
    Abstract: Novel tools and techniques are provided for implementing cantilevered power planes to provide a return current path for high-speed signals. In various embodiments, a semiconductor package includes a substrate core, a plurality of layers, and an AC coupler(s). The plurality of layers includes power, ground, and signal layers each layer disposed on or above the substrate core, each signal layer being disposed between a power layer and a ground layer, the power layer and the ground layer each providing a return path for high frequency (e.g., 1 kHz or greater) signals carried by each signal layer. Each dielectric layer is disposed between and in contact with a pair of power, ground, or signal layer. The AC coupler(s) is coupled to each of a power layer(s) and a ground layer(s), without any portion of any power layer that is near an edge of the substrate core being anchored to the substrate core.
    Type: Application
    Filed: December 6, 2024
    Publication date: March 20, 2025
    Inventors: Arun Ramakrishnan, Dharmendra Saraswat, Reza Sharifi, Sam Zhao, Sam Karikalan, Mayank Mayukh, Liming Tsau
  • Patent number: 12191243
    Abstract: Novel tools and techniques are provided for implementing cantilevered power planes to provide a return current path for high-speed signals. In various embodiments, a semiconductor package includes a substrate core, a plurality of layers, and an AC coupler(s). The plurality of layers includes power, ground, and signal layers each layer disposed on or above the substrate core, each signal layer being disposed between a power layer and a ground layer, the power layer and the ground layer each providing a return path for high frequency (e.g., 1 kHz or greater) signals carried by each signal layer. Each dielectric layer is disposed between and in contact with a pair of power, ground, or signal layer. The AC coupler(s) is coupled to each of a power layer(s) and a ground layer(s), without any portion of any power layer that is near an edge of the substrate core being anchored to the substrate core.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: January 7, 2025
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Arun Ramakrishnan, Dharmendra Saraswat, Reza Sharifi, Sam Zhao, Sam Karikalan, Mayank Mayukh, Liming Tsau
  • Publication number: 20240231878
    Abstract: Systems and methods are described for injecting chaos into an application based on a determination that network traffic will be at the application when the chaos is injected. In an example, a gateway can receive requests for applications in a system. The gateway can be configured to periodically insert a header into an application request that causes a proxy agent associated with the requested application to request chaos instructions from a server. When chaos instructions are requested, the server can determine whether and what kind of chaos to inject into the application. The server can send instructions to the proxy agent, which can inject chaos according to the instructions. A monitoring agent can then monitor traffic around the application to determine whether other applications and system components behave appropriately in response to the injected chaos.
    Type: Application
    Filed: March 31, 2023
    Publication date: July 11, 2024
    Inventors: Bomin Nie, Sam Zhao
  • Publication number: 20240151921
    Abstract: An apparatus includes a substrate that includes one or more routing layers, and an optical module coupled to the substrate. The optical module includes a photonic integrated circuit (PIC) and electronic integrated circuit (EIC), wherein the photonic integrated circuit is at least partially embedded within the substrate. The apparatus further includes a fiber optic coupler coupled to at least one of the substrate or PIC, wherein the PIC is configured to transmit or receive an optical signal via the fiber optic coupler.
    Type: Application
    Filed: January 17, 2024
    Publication date: May 9, 2024
    Inventors: Mayank Mayukh, Sam Zhao, Sam Karikalan, Reza Sharifi, Liming Tsau, Arun Ramakrishnan, Dharmendra Saraswat
  • Publication number: 20240145392
    Abstract: A substrate with differing dielectric constant materials is provided. The substrate includes a first ground plane, a second ground plane, a first conductive trace, a first material having a first dielectric constant, and a second material having a second dielectric constant. The first material is disposed between the first ground plane and the first conductive trace, and the second material is disposed between the second ground plane and at least part of the first conductive trace. The first dielectric constant is different from the second dielectric constant.
    Type: Application
    Filed: October 31, 2022
    Publication date: May 2, 2024
    Inventors: Dharmendra Saraswat, Mayank Mayukh, Reza Sharifi, Sam Zhao, Kwok Cheung Tsang, Vincent Huang, Jevon Yu, Sam Karikalan, Arun Ramakrishnan, Liming Tsau
  • Publication number: 20240128156
    Abstract: A semiconductor device with a hybrid bonded interface having microfluidic channels is provided. The semiconductor device includes a first die comprising a first passivation layer, wherein the first passivation layer includes one or more first trenches, and a second die comprising a second passivation layer, wherein the second passivation layer includes one or more second trenches. The first die is bonded to the second die via hybrid copper-to-copper bonding, wherein the one or more first trenches and the one or more second trenches form one or more channels.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Inventors: Sam Karikalan, Sam Zhao, Mayank Mayukh, Liming Tsau, Arun Ramakrishnan, Dharmendra Saraswat, Reza Sharifi
  • Patent number: 11906802
    Abstract: An apparatus includes a substrate that includes one or more routing layers, and an optical module coupled to the substrate. The optical module includes a photonic integrated circuit (PIC) and electronic integrated circuit (EIC), wherein the photonic integrated circuit is at least partially embedded within the substrate. The apparatus further includes a fiber optic coupler coupled to at least one of the substrate or PIC, wherein the PIC is configured to transmit or receive an optical signal via the fiber optic coupler.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: February 20, 2024
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Mayank Mayukh, Sam Zhao, Sam Karikalan, Reza Sharifi, Liming Tsau, Arun Ramakrishnan, Dharmendra Saraswat
  • Publication number: 20240038613
    Abstract: Novel tools and techniques are provided for implementing edge seal for bonded stacks of different size semiconductor devices. In various embodiments, a semiconductor device is provided that includes a composite structure and a sealant material. The composite structure includes two or more semiconductor devices that form a stacked configuration with one semiconductor device being disposed on or over each of one or more other semiconductor devices (of different size compared with that of the one semiconductor device) and with interface components of the one semiconductor device being bonded with corresponding interface components to each of the one or more other semiconductor devices in the stacked configuration. The sealant material is disposed along one or more surface portions of the composite structure to cover a region including at least portions of side surfaces of the composite structure that extend to cover at least each interface portion between stacked semiconductor devices.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Inventors: Sam Zhao, Sam Karikalan, Reza Sharifi, Mayank Mayukh, Arun Ramakrishnan, Dharmendra Saraswat, Liming Tsau
  • Publication number: 20240039141
    Abstract: A semiconductor package with integrated side wall antennas is provided. An apparatus includes two or more die layers that are bonded together, each of the two or more die layers comprising a top surface, bottom surface, and one or more side walls. A first side wall of the one or more side walls includes a first antenna array, the first antenna array comprising a first plurality of antenna array elements formed in at least one of the two or more die layers, wherein the first plurality of antenna array elements is at least partially exposed at the first side wall.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Inventors: Sam Karikalan, Sam Zhao, Mayank Mayukh, Dharmendra Saraswat, Liming Tsau, Arun Ramakrishnan, Reza Sharifi
  • Publication number: 20240038641
    Abstract: Novel tools and techniques are provided for implementing a substrate with an elastomer layer. The substrate might include one or more interconnects and an elastomer layer comprising at least one conductor. In some instances, the at least one conductor of the elastomer layer couples to at least one of the one or more interconnects of the substrate. Additionally, the at least one conductor is configured to couple at least one of the one or more interconnects of the substrate to a circuit board.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Inventors: Dharmendra Saraswat, Sam Karikalan, Sam Zhao, Mayank Mayukh, Arun Ramakrishnan, Reza Sharifi, Liming Tsau
  • Publication number: 20240038645
    Abstract: Novel tools and techniques are provided for implementing novel semiconductor package interconnection structure(s) between package substrate and PCB. In various embodiments, a semiconductor device comprises: a substrate; a plurality of posts; a plurality of solder anchor portions; and a plurality of solder balls. Each post is coupled at a proximal end to a conductive point on a layer of the substrate, and has a length extending along its axis between its proximal and distal ends and a width orthogonal to the length. Each solder anchor portion is coupled to the distal end of a corresponding post, and has a width that is larger than the width of a distal end of a pillar portion of the corresponding post. Each solder ball is disposed on and around a corresponding solder anchor portion, the solder balls and corresponding posts forming conductive interconnects between corresponding substrate conductive points and corresponding PCB contact points.
    Type: Application
    Filed: July 26, 2022
    Publication date: February 1, 2024
    Inventors: Sam Zhao, Sam Karikalan, Mayank Mayukh, Reza Sharifi, Liming Tsau, Roger Fratti, Arun Ramakrishnan, Dharmendra Saraswat
  • Publication number: 20240038724
    Abstract: Tools and techniques for a semiconductor package providing side wall interconnections are provided. An apparatus includes two or more die layers that are bonded together, the first 3D stacked die package comprising a top surface, bottom surface, and one or more side walls. A first side wall of the one or more side walls includes two or more side wall pads, wherein each side wall pad of the two or more side wall pads is coupled to an interconnect of a respective die layer of the two or more die layers.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Inventors: Sam Karikalan, Sam Zhao, Mayank Mayukh, Liming Tsau, Dharmendra Saraswat, Arun Ramakrishnan, Reza Sharifi
  • Publication number: 20230395444
    Abstract: Novel tools and techniques are provided for implementing mixed dielectric materials for improving signal integrity of integrated electronics packages or semiconductor packages. In various embodiments, a substrate for a semiconductor device includes: a first layer made of a first material; a second layer made of a second material; and a third layer disposed between the first and second layers, and that is made of a third material different from the first and second materials. In some cases, the first, second, and third layers each contains a plurality of gas-filled regions (e.g., but not limited to, an aerogel core of the third layer and/or polymer resin matrix embedded with hollow silica spheres or aerogel spheres of the first and second layers, or the like). Coaxial ground shields around signal lines in the substrate can be used to improve signal integrity. High dielectric constant lossy lines between signal lines can reduce crosstalk.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 7, 2023
    Inventors: Mayank Mayukh, Dharmendra Saraswat, Sam Karikalan, Liming Tsau, Sam Zhao, Arun Ramakrishnan, Reza Sharifi
  • Publication number: 20230367087
    Abstract: An apparatus includes a substrate that includes one or more routing layers, and an optical module coupled to the substrate. The optical module includes a photonic integrated circuit (PIC) and electronic integrated circuit (EIC), wherein the photonic integrated circuit is at least partially embedded within the substrate. The apparatus further includes a fiber optic coupler coupled to at least one of the substrate or PIC, wherein the PIC is configured to transmit or receive an optical signal via the fiber optic coupler.
    Type: Application
    Filed: May 10, 2022
    Publication date: November 16, 2023
    Inventors: Mayank Mayukh, Sam Zhao, Sam Karikalan, Reza Sharifi, Liming Tsau, Arun Ramakrishnan, Dharmendra Saraswat
  • Publication number: 20230369191
    Abstract: Novel tools and techniques are provided for implementing cantilevered power planes to provide a return current path for high-speed signals. In various embodiments, a semiconductor package includes a substrate core, a plurality of layers, and an AC coupler(s). The plurality of layers includes power, ground, and signal layers each layer disposed on or above the substrate core, each signal layer being disposed between a power layer and a ground layer, the power layer and the ground layer each providing a return path for high frequency (e.g., 1 kHz or greater) signals carried by each signal layer. Each dielectric layer is disposed between and in contact with a pair of power, ground, or signal layer. The AC coupler(s) is coupled to each of a power layer(s) and a ground layer(s), without any portion of any power layer that is near an edge of the substrate core being anchored to the substrate core.
    Type: Application
    Filed: May 13, 2022
    Publication date: November 16, 2023
    Inventors: Arun Ramakrishnan, Dharmendra Saraswat, Reza Sharifi, Sam Zhao, Sam Karikalan, Mayank Mayukh, Liming Tsau
  • Publication number: 20230369267
    Abstract: An apparatus includes an interposer comprising one or more area array interconnections, the one or more area array interconnections including a first type of area array interconnection and a second type of area array interconnection. The apparatus further includes a first die coupled to the interposer via the first type of area array interconnection, and a second die coupled to the interposer via the second type of area array interconnection, wherein the first type of area array interconnection is different from the second type of area array interconnection.
    Type: Application
    Filed: May 11, 2022
    Publication date: November 16, 2023
    Inventors: Sam Zhao, Mayank Mayukh, Sam Karikalan, Reza Sharifi, Arun Ramakrishnan, Liming Tsau, Dharmendra Saraswat
  • Publication number: 20230352383
    Abstract: Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly, for implementing a semiconductor package or a chip package including a core or a multilayer core having one or more variable width vias or one or more offset vias. In various embodiments, an apparatus includes a substrate. The substrate includes a core. The core may include one or more vias extending through the core. At least one via of the one or more vias includes a cross-section that varies along a length of the at least one via as the via extends through the core. The cross-section of the via may vary based on at least one of varying a width of the at least one via or offsetting a first portion of the at least one via from a second portion of the at least one via.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Inventors: Dharmendra Saraswat, Arun Ramakrishnan, Sam Zhao, Sam Karikalan, Mayank Mayukh, Liming Tsau, Reza Sharifi
  • Patent number: 11758016
    Abstract: Embodiments of the present disclosure relate to techniques for providing a remoted application to a client device over a network. Certain embodiments involve receiving, by a web server and from the client device, a request for the remoted application. The request may comprise a tag which identifies one or more attributes of the remoted application. Embodiments further involve launching, by the web server and based on the tag, the remoted application. Embodiments further involve providing, by the web server and to the client device, a video stream of the remoted application. The video stream of the remoted application may comprise one or more images rendered based on raw data of the remoted application. Embodiments further involve receiving, by the web server and from the client device, user input and providing, by the web server and based on the user input, application input to the remoted application.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: September 12, 2023
    Assignee: VMWARE, INC.
    Inventors: Shengbo Teng, Sam Zhao, Wen Wang, Nan Wang, Jingtao Zhang