Abstract: A radar system includes a transmitter including a power amplifier (PA) for amplifying a local oscillator (LO) signal, to generate an amplified signal. The radar system also includes a receiver including an IQ generator for generating an I signal based on the LO signal and for generating a Q signal based on the LO signal and a low noise amplifier (LNA) for amplifying a looped back signal, to generate a receiver signal. The receiver also includes a first mixer for mixing the receiver signal and the I signal, to generate a baseband I signal and a second mixer for mixing the receiver signal and the Q signal, to generate a baseband Q signal. Additionally, the radar system includes a waveguide loopback for guiding the amplified signal from the transmitter to the receiver as the looped back signal.

Abstract: An integrated circuit includes a passive component having a first metal feature and a second metal feature, the first metal feature and the second metal feature defining an interior area therebetween. The integrated circuit also includes set of spaced metal fill lines extending across the interior area and oriented to carry current orthogonal to current carried by the first metal feature and second metal feature.

Abstract: A radar system includes a transmitter including a power amplifier (PA) for amplifying a local oscillator (LO) signal, to generate an amplified signal. The radar system also includes a receiver including an IQ generator for generating an I signal based on the LO signal and for generating a Q signal based on the LO signal and a low noise amplifier (LNA) for amplifying a looped back signal, to generate a receiver signal. The receiver also includes a first mixer for mixing the receiver signal and the I signal, to generate a baseband I signal and a second mixer for mixing the receiver signal and the Q signal, to generate a baseband Q signal. Additionally, the radar system includes a waveguide loopback for guiding the amplified signal from the transmitter to the receiver as the looped back signal.

Abstract: A radar system includes a transmitter including a power amplifier (PA) for amplifying a local oscillator (LO) signal, to generate an amplified signal. The radar system also includes a receiver including an IQ generator for generating an I signal based on the LO signal and for generating a Q signal based on the LO signal and a low noise amplifier (LNA) for amplifying a looped back signal, to generate a receiver signal. The receiver also includes a first mixer for mixing the receiver signal and the I signal, to generate a baseband I signal and a second mixer for mixing the receiver signal and the Q signal, to generate a baseband Q signal. Additionally, the radar system includes a waveguide loopback for guiding the amplified signal from the transmitter to the receiver as the looped back signal.

Abstract: A radar system includes a transmitter including a power amplifier (PA) for amplifying a local oscillator (LO) signal, to generate an amplified signal. The radar system also includes a receiver including an IQ generator for generating an I signal based on the LO signal and for generating a Q signal based on the LO signal and a low noise amplifier (LNA) for amplifying a looped back signal, to generate a receiver signal. The receiver also includes a first mixer for mixing the receiver signal and the I signal, to generate a baseband I signal and a second mixer for mixing the receiver signal and the Q signal, to generate a baseband Q signal. Additionally, the radar system includes a waveguide loopback for guiding the amplified signal from the transmitter to the receiver as the looped back signal.

Abstract: A circuit containing a pair of charge pumps and an active filter receives outputs of a phase frequency detector used in a phase locked loop. The charge pump is implemented using switches and resistors to reduce performance variations due to component mismatches. The loop filter includes a resistor and a capacitor coupled in series, the resistor and the capacitor determining a zero of the transfer function of the loop filter. The charge pump circuit simultaneously injects a first current pulse at a first node of the loop filter and a second current pulse at a second node formed by a junction of the resistor and the capacitor. The polarity of the first current pulse is the opposite of the polarity of the second current pulse. Multiplication of the capacitance of the capacitor is thereby achieved, enabling implementation of the loop filter in integrated circuit form.

Abstract: A loop filter of a phase-locked loop (PLL) that uses a current-controlled oscillator (CCO) includes a capacitor, a voltage-to-current (V-to-I) converter, and a charge pump. The input node of the loop filter receives a first current from an external charge pump. The combination of the capacitor and the V-to-I converter generates a first component of the output current of the loop filter based on the first current. The charge pump of the loop filter generates a second component of the output current. The loop filter is implemented without the need for a zero-frequency-determining resistor, the resistor instead being realized by the product of the first current, the second component of the output current and the transconductance of the V-to-I converter. Phase noise reduction in the PLL, as well as implementation of the loop filter with a smaller area, are thus made possible.

Abstract: A loop filter of a phase-locked loop (PLL) that uses a current-controlled oscillator (CCO) includes a capacitor, a voltage-to-current (V-to-I) converter, and a charge pump. The input node of the loop filter receives a first current from an external charge pump. The combination of the capacitor and the V-to-I converter generates a first component of the output current of the loop filter based on the first current. The charge pump of the loop filter generates a second component of the output current. The loop filter is implemented without the need for a zero-frequency-determining resistor, the resistor instead being realized by the product of the first current, the second component of the output current and the transconductance of the V-to-I converter. Phase noise reduction in the PLL, as well as implementation of the loop filter with a smaller area, are thus made possible.

Abstract: A continuous-time sigma-delta analog to digital converter (CTSD ADC) includes a comparator that samples the time integral of an analog signal at each rising edge and falling edge of a sampling clock. A feedback block, operating as a digital to analog converter, receives the outputs of the comparator and generates corresponding analog signals also at each rising and falling edge of the sampling clock. The feedback blocks are implemented as either switched-resistor or switched-current circuits. High signal-to-noise ratio (SNR) is achieved in the CTSD ADC without the need to use very high sampling clock frequencies. Compensation for excess loop delay is provided using a local feedback technique. In an embodiment, the sigma delta modulator in the CTSD ADC is implemented as a second order loop, and the comparator as a two-level comparator.

Abstract: A continuous-time sigma-delta analog to digital converter (CTSD ADC) includes a comparator that samples the time integral of an analog signal at each rising edge and falling edge of a sampling clock. A feedback block, operating as a digital to analog converter, receives the outputs of the comparator and generates corresponding analog signals also at each rising and falling edge of the sampling clock. The feedback blocks are implemented as either switched-resistor or switched-current circuits. High signal-to-noise ratio (SNR) is achieved in the CTSD ADC without the need to use very high sampling clock frequencies. Compensation for excess loop delay is provided using a local feedback technique. In an embodiment, the sigma delta modulator in the CTSD ADC is implemented as a second order loop, and the comparator as a two-level comparator.

Abstract: A circuit containing a pair of charge pumps and an active filter receives outputs of a phase frequency detector used in a phase locked loop. The charge pump is implemented using switches and resistors to reduce performance variations due to component mismatches. The loop filter includes a resistor and a capacitor coupled in series, the resistor and the capacitor determining a zero of the transfer function of the loop filter. The charge pump circuit simultaneously injects a first current pulse at a first node of the loop filter and a second current pulse at a second node formed by a junction of the resistor and the capacitor. The polarity of the first current pulse is the opposite of the polarity of the second current pulse. Multiplication of the capacitance of the capacitor is thereby achieved, enabling implementation of the loop filter in integrated circuit form.

Abstract: A circuit includes a digital-to-analog converter (DAC), coupled to a power supply, that provides a first current at a first output terminal of the DAC and a second current at a second output terminal of the DAC, the first current being differential to the second current; a first circuit, coupled to the first output terminal of the DAC and to the second output terminal of the DAC, that generates a first voltage and a second voltage, the first voltage being non-linear with respect to the first current and the second voltage being non-linear with respect to the second current; and an attenuator coupled to the first circuit, and responsive to the first voltage and the second voltage to attenuate an input signal of the attenuator and to generate linear attenuation characteristics in decibels with respect to the first current and the second current.

Abstract: A fast locking delay-locked loop (DLL), which can also operate as a clock data recovery circuit (CDR), includes a delay chain, a sampling circuit and a transition detector. An input signal and delayed versions of the input signal generated by the delay chain are sampled by the sampling circuit. The outputs of the sampling circuit are provided to a transition detector which selects one of the input signal and its delayed versions determined to have signal transitions most closely aligned with a sampling edge of a clock. The selected signal and the clock are provided as inputs to a phase discriminator which generates an error signal representing a level of phase mismatch between the inputs. The error signal is fed back to the sampling circuit to maintain phase lock between the clock signal and the input bit stream.

Abstract: A circuit includes a digital-to-analog converter (DAC), coupled to a power supply, that provides a first current at a first output terminal of the DAC and a second current at a second output terminal of the DAC, the first current being differential to the second current; a first circuit, coupled to the first output terminal of the DAC and to the second output terminal of the DAC, that generates a first voltage and a second voltage, the first voltage being non-linear with respect to the first current and the second voltage being non-linear with respect to the second current; and an attenuator coupled to the first circuit, and responsive to the first voltage and the second voltage to attenuate an input signal of the attenuator and to generate linear attenuation characteristics in decibels with respect to the first current and the second current.

Abstract: A low noise current steering digital-to-analog converter (DAC). The DAC includes a current reference for generating a bias current that biases a set of current elements. The set of current elements includes a reference element. The current reference includes a reference amplifier and a reference arm. The reference arm includes a reference resistor and the reference element. The DAC further includes a switch periodically coupling each current element including the reference element, to the reference resistor and an output of the DAC. This rotates the set of current elements and attenuates flicker noise from each of the set of current elements.

Abstract: A low noise current steering digital-to-analog converter (DAC). The DAC includes a current reference for generating a bias current that biases a set of current elements. The set of current elements includes a reference element. The current reference includes a reference amplifier and a reference arm. The reference arm includes a reference resistor and the reference element. The DAC further includes a switch periodically coupling each current element including the reference element, to the reference resistor and an output of the DAC. This rotates the set of current elements and attenuates flicker noise from each of the set of current elements.

Abstract: A VCO buffer circuit comprising a first loading means receiving a first signal for loading the VCO at a first input node; a second loading means receiving a second signal for loading the VCO at a second input node; a third loading means coupled to said first loading means for loading the VCO at third input node to thereby balance a load distribution on three nodes of VCO. At least three current controlling means are coupled to each other to form a symmetrical configuration and receive input signals from said first and second loading means for minimizing variations in the oscillation frequency of the VCO. A buffering means is connected to the output of the controlling means for buffering the output of the current controlling means.

Abstract: A first order temperature compensated reference current generator includes a current device providing a controlled current, a startup circuit connected to the current device for initiating operation of the current device, and a current definition mechanism driven by the current device for supplying a current which is independent of temperature, process and individual temperature coefficients circuit elements used. The current definition mechanism incorporates voltage controlled resistors driven by a predetermined voltage and having a predetermined temperature coefficient.

Abstract: A first order temperature compensated reference current generator includes a current device providing a controlled current, a startup circuit connected to the current device for initiating operation of the current device, and a current definition mechanism driven by the current device for supplying a current which is independent of temperature, process and individual temperature coefficients circuit elements used. The current definition mechanism incorporates voltage controlled resistors driven by a predetermined voltage and having a predetermined temperature coefficient.

Abstract: A VCO buffer circuit comprising a first loading means receiving a first signal for loading the VCO at a first input node; a second loading means receiving a second signal for loading the VCO at a second input node; a third loading means coupled to said first loading means for loading the VCO at third input node to thereby balance a load distribution on three nodes of VCO. At least three current controlling means are coupled to each other to form a symmetrical configuration and receive input signals from said first and second loading means for minimizing variations in the oscillation frequency of the VCO. A buffering means is connected to the output of the controlling means for buffering the output of the current controlling means.