Abstract: A system for testing multiple disparate or similar devices independently and simultaneously using different types of device probes is disclosed. The system includes real-time, bi-directional/asynchronous communication and interaction between the system components.

Abstract: An operator dashboard (user interface) used for testing disparate devices simultaneously and independently and further capable of asynchronous communication is disclosed.

Abstract: A core testing executor/processor for testing a plurality of devices simultaneously using virtualization containers to connect to interfaces of corresponding devices under test is disclosed.

Abstract: A system for testing multiple set top boxes independently and simultaneously using different types of device probes is disclosed. The system includes real-time, bi-directional/asynchronous communication and interaction between system components.

Abstract: A method or device handles memory management faults in a device having a digital signal processor (“DSP”) and a microprocessor. The DSP includes a memory management unit (“DSP MMU”) to manage memory access by the DSP, and the DSP and the microprocessor access shared physical memory. Upon the DSP executing an instruction attempting to access a virtual address wherein the virtual address is invalid, a page fault interrupt is generated by the DSP MMU. A microprocessor interrupt handler in the microprocessor is activated in direct response to the page fault interrupt. Thereafter in the microprocessor, a translation lookaside buffer (“TLB”) entry is created in the DSP MMU, which includes a valid mapping between the virtual address and a page of physical memory. After creating the TLB entry, the microprocessor indicates to the DSP that the access by the DSP of the virtual address is completed.

Abstract: A method or device handles memory management faults in a device having a digital signal processor (“DSP”) and a microprocessor. The DSP includes a memory management unit (“DSP MMU”) to manage memory access by the DSP, and the DSP and the microprocessor access shared physical memory. Upon the DSP executing an instruction attempting to access a virtual address wherein the virtual address is invalid, a page fault interrupt is generated by the DSP MMU. A microprocessor interrupt handler in the microprocessor is activated in direct response to the page fault interrupt. Thereafter in the microprocessor, a translation lookaside buffer (“TLB”) entry is created in the DSP MMU, which includes a valid mapping between the virtual address and a page of physical memory. After creating the TLB entry, the microprocessor indicates to the DSP that the access by the DSP of the virtual address is completed.

Abstract: A subscriber device capable of Voice over Internet Protocol (VoIP) communication via a wireless connection with an 802.11 access point to an Internet Protocol (IP) based network includes a codec for encoding a signal into a Real Time Protocol (RTP) packet and a controller for controlling a bit-rate at which the codec encodes the signal. The codec encodes the signal at a first bit-rate during normal transmissions and encodes the signal at a second bit-rate lower than the first bit-rate upon occurrence of a predetermined triggering event.

Abstract: Disclosed above are various embodiments of VoIP communication systems that utilize low cost IP phones that rely on a centralized VoIP controller for much of the processing. Reducing the processing taking place on an IP phone may reduce the number of components that need to be on the IP phone which may result in a less expensive IP phone in terms of both cost and power. When the IP phone is embodied as a WIPP, the reduced processing may also result in more efficient communication between the WIPP and an AP. The increased communication efficiency may result in less power being used by the WIPP and effectively extend the battery life. Since a number of redundant components have been centralized, the VoIP system as a whole may be less costly. Also, centralized control may provide greater functionality and versatility in the setup and configuration of a VoIP communication system.

Abstract: A fax-aware telephone for handling facsimile transmissions over a computer network, such as the Internet, that includes a facsimile processing unit for handling an incoming or outgoing facsimile call, a voice processing unit for handling an incoming or outgoing voice call, a memory unit for storing an incoming facsimile transmission, and a file transfer protocol client for transferring a facsimile transmission to the computer network, an external storage device, or to a printer driver. The fax-aware telephone handles a facsimile call and a voice call together over a single data line from a computer network.