Patents by Inventor Samarth S. Modi

Samarth S. Modi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Simplified, extendable, edge-based watchdog for DLL
    Patent number: 8030980
    Abstract: A delay locked loop (DLL) is provided. Within this DLL is a watchdog circuit that determines whether harmonic lock is present. Based on this measurement, the watchdog circuit can provide adjustments to the DLL so as to change the length of the delay of the delay line to bring it within a predetermined range.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: October 4, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Samarth S. Modi, Nitin Agarwal, Mrityunjay Kr. Baranwal
  • Wide range delay cell
    Patent number: 7969219
    Abstract: A delay cell with a wider delay range is provided. The delay cell employs frequency dependent current source to generate the majority of the delay of the cell, while a control circuit (which is generally a current source that is controlled by a control voltage) provides additional delay. Thus, the delay cell provided here can be used to improve the performance of delay locked loops (DLLs) and other circuits.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: June 28, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Jagannathan Venkataraman, Vivesvaraya A. Pentakota, Samarth S. Modi
  • Multibit recyclic pipelined ADC architecture
    Patent number: 7948410
    Abstract: An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit converter pair, a third hold switch, and an M-bit converter pair. The sample receives an input signal and is actuated by a sample signal. The sampling capacitor is coupled to the sample switch. The amplifier has a first input terminal that is coupled to the sampling capacitor. The feedback branches are coupled between the output terminal of the amplifier and the first input terminal of the amplifier, with each feedback branch including a feedback capacitor, and a first hold switch that is coupled to the feedback capacitor. The second hold switch is coupled to the sampling switch. The N-bit converter pair is coupled to the sampling switch and to the second hold switch. The third hold switch is coupled to at least one of the feedback branches, and the M-bit converter pair is coupled to the output terminal of the amplifier and to the third hold switch.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: May 24, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Jagannathan Venkataraman, Visvesvaraya A. Pentakota, Sandeep K. Oswal, Samarth S. Modi, Shagun Dusad
  • MULTIBIT RECYCLIC PIPELINED ADC ARCHITECTURE
    Publication number: 20110012764
    Abstract: An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit converter pair, a third hold switch, and an M-bit converter pair. The sample receives an input signal and is actuated by a sample signal. The sampling capacitor is coupled to the sample switch. The amplifier has a first input terminal that is coupled to the sampling capacitor. The feedback branches are coupled between the output terminal of the amplifier and the first input terminal of the amplifier, with each feedback branch including a feedback capacitor, and a first hold switch that is coupled to the feedback capacitor. The second hold switch is coupled to the sampling switch. The N-bit converter pair is coupled to the sampling switch and to the second hold switch. The third hold switch is coupled to at least one of the feedback branches, and the M-bit converter pair is coupled to the output terminal of the amplifier and to the third hold switch.
    Type: Application
    Filed: December 16, 2009
    Publication date: January 20, 2011
    Applicant: Texas Instruments Incorporated
    Inventors: Jagannathan Venkataraman, Visvesvaraya A. Pentakota, Sandeep K. Oswal, Samarth S. Modi, Shagun Dusad
  • SIMPLIFIED, EXTENDABLE, EDGE-BASED WATCHDOG FOR DLL
    Publication number: 20100164574
    Abstract: A delay locked loop (DLL) is provided. Within this DLL is a watchdog circuit that determines whether harmonic lock is present. Based on this measurement, the watchdog circuit can provide adjustments to the DLL so as to change the length of the delay of the delay line to bring it within a predetermined range.
    Type: Application
    Filed: November 23, 2009
    Publication date: July 1, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Samarth S. Modi, Nitin Agarwal, Mrityunjay Kr Baranwal
  • WIDE RANGE DELAY CELL
    Publication number: 20100148838
    Abstract: A delay cell with a wider delay range is provided. The delay cell employs frequency dependent current source to generate the majority of the delay of the cell, while a control circuit (which is generally a current source that is controlled by a control voltage) provides additional delay. Thus, the delay cell provided here can be used to improve the performance of delay locked loops (DLLs) and other circuits.
    Type: Application
    Filed: November 23, 2009
    Publication date: June 17, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Jagannathan Venkataraman, Vivesvaraya A. Pentakota, Samarth S. Modi