Abstract: Hardware and/or software that dynamically enables or disables CRC and/or adjust voltage level of power supply to a physical layer block on a host by determining an optimum tradeoff between power and performance. The hardware and/or software decreases the voltage level for the power supply and enables CRC to compensate signal errors (e.g., errors from signal integrity issues). Hardware and/or software dynamically adjusts voltage level of the power supply rail based on the throughput or speed of the DDR link. In some examples, depending on read or write operations, the voltage level of the power supply rail is adjusted.

Abstract: In a memory subsystem, the memory device and memory controller can exchange data at either a first burst length or a second burst length longer than the first burst length. The memory subsystem includes a cache or other circuitry to buffer ECC (error checking and correction) bits. The memory controller can generate a data read request to read data from memory and a separate ECC read request to read the ECC bits. The ECC cache can buffer ECC bits for multiple data read requests. The memory controller can dynamically switch the ECC read request between the first burst length and the second burst length based on usage of the ECC cache.

Abstract: Techniques and mechanisms for managing a delivery of power to a resource of an input/output (I/O) interface. In an embodiment, a first link of a plurality of communication links is monitored. Of the plurality of links, a first set of resources of the I/O interface is to support communication only via the first link. One or more other resources of the I/O interface are for supporting communications of another link of the plurality of links. In another embodiment, a resource of the first set of resources is decoupled from a power supply in response to detecting a total number of active lanes of the first link, decoupling.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Abstract: Techniques and mechanisms for managing a delivery of power to a resource of an input/output (I/O) interface. In an embodiment, a first link of a plurality of communication links is monitored. Of the plurality of links, a first set of resources of the I/O interface is to support communication only via the first link. One or more other resources of the I/O interface are for supporting communications of another link of the plurality of links. In another embodiment, a resource of the first set of resources is decoupled from a power supply in response to detecting a total number of active lanes of the first link, decoupling.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Abstract: Method and apparatus to scrub memory is disclosed. A patrol request, for example a read/write request, may be raised to the memory command scheduler in an out of order memory controller to scrub the memory. The patrol read/write request may be raised as and when patrol interval timer expires. The patrol read/write request may also be raised based on presence of a transaction in-flight to the memory, retry response from the memory command scheduler and correctable or non-correctable error response from the memory command scheduler. An interrupt may be raised to a processor upon completion response from the memory command scheduler.

Abstract: A method and apparatus for parallelizing address-mapping and page referencing in a memory controller. The page referencing may apply an input address to two separate content addressable memory components along with masks from a configuration register identifying rank-bank bits, page status bits and non-column bits. The content addressable memories each determine if matching content is present generating a ‘hit’ or ‘miss.’ The hit and miss indicators are applied to combinational logic to determine whether to generate a CAS, RAS-CAS or PRE-RAS-CAS indicator.

Abstract: A method and apparatus for parallelizing address-mapping and page referencing in a memory controller. The page referencing may apply an input address to two separate content addressable memory components along with masks from a configuration register identifying rank-bank bits, page status bits and non-column bits. The content addressable memories each determine if matching content is present generating a ‘hit’ or ‘miss.’ The hit and miss indicators are applied to combinational logic to determine whether to generate a CAS, RAS-CAS or PRE-RAS-CAS indicator.