Abstract: A power delivery sub-system included in a computer system employs a primary voltage regulator circuit that generates a primary supply voltage on a primary power supply node. The power delivery sub-system also includes multiple bypass voltage regulator circuits that source corresponding bypass currents to a local power supply nodes in an integrated circuit. The integrated circuit includes multiple circuit blocks coupled to corresponding ones of the local power supply nodes, and multiple local voltage regulator circuits coupled to the primary power supply node. When a voltage level of a given local power supply node drops below a threshold value, a corresponding local voltage regulator circuit sources a supply current to the given local power supply node.

Abstract: A cell layout that may be implemented in FinFET devices or other FET devices is disclosed. The cell layout includes a control signal route that passes from a first device into backside layers and then underneath a second device. The control signal route then routes back to topside metal layers through inactive transistors that are implemented as via structures on the other side of the second device. Connection to the gate of the second device may then be completed through the topside metal layers. The disclosed control signal route provides a low resistance path that reduces RC delay in the devices in the cell layout.

Abstract: A standard cell layout that may be implemented in FinFET devices or nanosheet FET devices is disclosed. The standard cell layout includes power supply connections from both a topside metal layer and a backside metal layer. A device in the standard cell may be connected to both the topside metal layer and the backside metal layer. Source/drain regions of the device may be connected the metal layers using via contacts within the standard cell layout. Connections to power supply rails from the topside metal layer and the backside metal layer may also be included in the standard cell layout. The rails may be connected to a power supply such that the power supply provides power to the device through both the topside and backside metal layers.

Abstract: A device is disclosed that includes a circuit block coupled to a local power node, and a power gating circuit coupled between the local power node and a global power supply. In one embodiment, the power gating circuit includes a first plurality of first switching devices with a first threshold voltage, and a second plurality of second switching devices with a second threshold voltage that is different from the first voltage threshold. The power gating circuit may isolate the local power node from the global power supply based on an isolation signal.

Abstract: Embodiments of an electromigration (EM) check scheme to reduce a pessimism on current density limits by checking wire context. This methodology, in an embodiment, includes applying existing electronic design automation (EDA) flows and tools to identify potentially-failing wires based on a worst-case EM check using conservative foundry current density limits. A more accurate, context-specific check can be performed on the potentially-failing wires to eliminate one or more of the potentially-failing wires if those wires do not experience worst-case conditions and meet current density limits based on an actual context of those wires. A designer can correct remaining wires which are not eliminated by the context-specific check.

Abstract: There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer and electrical circuit optimizer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter and for modifying a component size of the electrical circuit to alter gate timing characteristics of the electrical circuit based upon the at least one of the signal arrival time and the signal required time.

Abstract: A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.

Abstract: A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.

Abstract: There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer and electrical circuit optimizer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter and for modifying a component size of the electrical circuit to alter gate timing characteristics of the electrical circuit based upon the at least one of the signal arrival time and the signal required time.

Abstract: Embodiments of the invention provide a method, computer program product, etc. for analysis techniques to reduce simulations to characterize the effect of variations in transistor circuits. A method of simulating transistors in an integrated circuit begins by reducing a group of parallel transistors to a single equivalent transistor. The equivalent transistor is subsequently simulated, wherein only a portion of the parallel transistors are simulated. Next, the integrated circuit is divided into channel-connected components and simulated for the channel-connected components. A table is created for each type of channel-connected component; and parameterized across chip variation equations are calculated from results of the integrated circuit simulation. Moreover, table entries are created, which include a number of transistor types, a number of unique transistor primitive patterns, and/or a number of paths through each of the transistor primitive patterns.

Abstract: There is provided a system and method for statistical timing analysis of an electrical circuit. The system includes at least one parameter input, a statistical static timing analyzer, and at least one output. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter. The at least one output is for outputting the at least one of the signal arrival time and the signal required time.

Abstract: There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer and electrical circuit optimizer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter and for modifying a component size of the electrical circuit to alter gate timing characteristics of the electrical circuit based upon the at least one of the signal arrival time and the signal required time.

Abstract: There is provided a system and method for statistical timing analysis of an electrical circuit. The system includes at least one parameter input, a statistical static timing analyzer, and at least one output. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter. The at least one output is for outputting the at least one of the signal arrival time and the signal required time.