Abstract: A cap chip or high density reroute layer for use in a stacked microelectronic module. A first set of electrically conductive reroute layers are defined on a sacrificial substrate. One or more stud bump columns are defined on an exposed conducive pad on a conductive reroute layer. One or more active or passive electronic elements, or both may be electrically coupled to one or more exposed conductive pads. The layer is encapsulated in an encapsulant and the stud bump columns exposed by removing a portion of the encapsulant. A second set of electrically conductive reroute layers is defined on the layer and electrically coupled to the stud bumps. The sacrificial substrate is removed to provide a cap chip or reroute layer.

Abstract: A cap chip or high density reroute layer for use in a stacked microelectronic module. A first set of electrically conductive reroute layers are defined on a sacrificial substrate. One or more stud bump columns are defined on an exposed conducive pad on a conductive reroute layer. One or more active or passive electronic elements, or both may be electrically coupled to one or more exposed conductive pads. The layer is encapsulated in an encapsulant and the stud bump columns exposed by removing a portion of the encapsulant. A second set of electrically conductive reroute layers is defined on the layer and electrically coupled to the stud bumps. The sacrificial substrate is removed to provide a cap chip or reroute layer.

Abstract: A high capacity, secure and tamper-resistant computer data memory device. The device uses a plurality of dedicated memory controller elements in communication with an anti-tamper module that generates a tamper response when a predetermined tamper event occurs. The tamper response may be provided as the erasure or zeroization of the contents of a memory in the devices such as erasing one or more encryption keys. The elements of the device are preferably provided in a stacked configuration with rerouted I/O pads to obfuscate the I/O and function of the devices in the stack. In one embodiment, a data transfer governance means is provided. In a further embodiment, a current negotiation means is disclosed to permit the device to request a predetermined current from a host device. In a yet further embodiment, a portable safe house computing device is provided.

Abstract: The disclosed invention comprises a substrate having one or more conductive metal traces comprising one or more electrical access leads terminating on a lateral surface of the substrate. A layer or stack of layers comprising one or more integrated circuit chips having one or more access leads in electrical connection with one or more integrated circuit bond pads on the one or more integrated circuit chips is bonded to the substrate. The surface area of the layers is less than the surface area of the substrate so as to define one or more component surface areas on the substrate. The access leads of the layers are oriented to be substantially coplanar and in vertical registration with the access leads of the substrate access leads.

Abstract: A stackable neo-layer comprising one or more embedded discrete electrical components is provided. A plurality of conductive traces, some of which terminate at a peripheral edge of the layer, are formed on sacrificial substrate in a series of process steps and discrete electrical components such as thick film components or wire bonded components are attached thereto. An under-bump metal process step is disclosed and provides for solder attachment at desired contact pad locations. The layer is encapsulated in a potting material and thinned to provide a thin, stackable layer. When assembled into a stack of layers, the electrically conductive traces terminating at the edge of the layer can be electrically connected by means of electroplating using a T-connect.

Abstract: A stackable neo-layer comprising one or more embedded discrete electrical components is provided. A plurality of conductive traces, some of which terminate at a peripheral edge of the layer, are formed on sacrificial substrate in a series of process steps and discrete electrical components such as thick film components or wire bonded components are attached thereto. An under-bump metal process step is disclosed and provides for solder attachment at desired contact pad locations. The layer is encapsulated in a potting material and thinned to provide a thin, stackable layer. When assembled into a stack of layers, the electrically conductive traces terminating at the edge of the layer can be electrically connected by means of electroplating using a T-connect.